Lines Matching refs:i2c
3 * i2c-xiic.c
24 #include <linux/i2c.h>
27 #include <linux/platform_data/i2c-xiic.h>
34 #define DRIVER_NAME "xiic-i2c"
148 * setting i2c clock frequency for the line.
235 #define xiic_tx_space(i2c) ((i2c)->tx_msg->len - (i2c)->tx_pos)
236 #define xiic_rx_space(i2c) ((i2c)->rx_msg->len - (i2c)->rx_pos)
238 static int xiic_start_xfer(struct xiic_i2c *i2c, struct i2c_msg *msgs, int num);
239 static void __xiic_start_xfer(struct xiic_i2c *i2c);
249 static inline void xiic_setreg8(struct xiic_i2c *i2c, int reg, u8 value)
251 if (i2c->endianness == LITTLE)
252 iowrite8(value, i2c->base + reg);
254 iowrite8(value, i2c->base + reg + 3);
257 static inline u8 xiic_getreg8(struct xiic_i2c *i2c, int reg)
261 if (i2c->endianness == LITTLE)
262 ret = ioread8(i2c->base + reg);
264 ret = ioread8(i2c->base + reg + 3);
268 static inline void xiic_setreg16(struct xiic_i2c *i2c, int reg, u16 value)
270 if (i2c->endianness == LITTLE)
271 iowrite16(value, i2c->base + reg);
273 iowrite16be(value, i2c->base + reg + 2);
276 static inline void xiic_setreg32(struct xiic_i2c *i2c, int reg, int value)
278 if (i2c->endianness == LITTLE)
279 iowrite32(value, i2c->base + reg);
281 iowrite32be(value, i2c->base + reg);
284 static inline int xiic_getreg32(struct xiic_i2c *i2c, int reg)
288 if (i2c->endianness == LITTLE)
289 ret = ioread32(i2c->base + reg);
291 ret = ioread32be(i2c->base + reg);
295 static inline void xiic_irq_dis(struct xiic_i2c *i2c, u32 mask)
297 u32 ier = xiic_getreg32(i2c, XIIC_IIER_OFFSET);
299 xiic_setreg32(i2c, XIIC_IIER_OFFSET, ier & ~mask);
302 static inline void xiic_irq_en(struct xiic_i2c *i2c, u32 mask)
304 u32 ier = xiic_getreg32(i2c, XIIC_IIER_OFFSET);
306 xiic_setreg32(i2c, XIIC_IIER_OFFSET, ier | mask);
309 static inline void xiic_irq_clr(struct xiic_i2c *i2c, u32 mask)
311 u32 isr = xiic_getreg32(i2c, XIIC_IISR_OFFSET);
313 xiic_setreg32(i2c, XIIC_IISR_OFFSET, isr & mask);
316 static inline void xiic_irq_clr_en(struct xiic_i2c *i2c, u32 mask)
318 xiic_irq_clr(i2c, mask);
319 xiic_irq_en(i2c, mask);
322 static int xiic_clear_rx_fifo(struct xiic_i2c *i2c)
328 for (sr = xiic_getreg8(i2c, XIIC_SR_REG_OFFSET);
330 sr = xiic_getreg8(i2c, XIIC_SR_REG_OFFSET)) {
331 xiic_getreg8(i2c, XIIC_DRR_REG_OFFSET);
333 dev_err(i2c->dev, "Failed to clear rx fifo\n");
341 static int xiic_wait_tx_empty(struct xiic_i2c *i2c)
347 for (isr = xiic_getreg32(i2c, XIIC_IISR_OFFSET);
349 isr = xiic_getreg32(i2c, XIIC_IISR_OFFSET)) {
351 dev_err(i2c->dev, "Timeout waiting at Tx empty\n");
361 * @i2c: Pointer to the xiic device structure
371 static int xiic_setclk(struct xiic_i2c *i2c)
377 dev_dbg(i2c->adap.dev.parent,
378 "%s entry, i2c->input_clk: %ld, i2c->i2c_clk: %d\n",
379 __func__, i2c->input_clk, i2c->i2c_clk);
382 if (!i2c->i2c_clk || !i2c->input_clk)
385 clk_in_mhz = DIV_ROUND_UP(i2c->input_clk, 1000000);
387 switch (i2c->i2c_clk) {
398 dev_warn(i2c->adap.dev.parent, "Unsupported scl frequency\n");
410 reg_val = (DIV_ROUND_UP(i2c->input_clk, 2 * i2c->i2c_clk)) - 7;
414 xiic_setreg32(i2c, XIIC_THIGH_REG_OFFSET, reg_val - 1);
417 xiic_setreg32(i2c, XIIC_TLOW_REG_OFFSET, reg_val - 1);
421 xiic_setreg32(i2c, XIIC_TSUSTA_REG_OFFSET, reg_val - 1);
425 xiic_setreg32(i2c, XIIC_TSUSTO_REG_OFFSET, reg_val - 1);
429 xiic_setreg32(i2c, XIIC_THDSTA_REG_OFFSET, reg_val - 1);
433 xiic_setreg32(i2c, XIIC_TSUDAT_REG_OFFSET, reg_val - 1);
437 xiic_setreg32(i2c, XIIC_TBUF_REG_OFFSET, reg_val - 1);
440 xiic_setreg32(i2c, XIIC_THDDAT_REG_OFFSET, 1);
445 static int xiic_reinit(struct xiic_i2c *i2c)
449 xiic_setreg32(i2c, XIIC_RESETR_OFFSET, XIIC_RESET_MASK);
451 ret = xiic_setclk(i2c);
456 xiic_setreg8(i2c, XIIC_RFD_REG_OFFSET, IIC_RX_FIFO_DEPTH - 1);
459 xiic_setreg8(i2c, XIIC_CR_REG_OFFSET, XIIC_CR_TX_FIFO_RESET_MASK);
462 xiic_setreg8(i2c, XIIC_CR_REG_OFFSET, XIIC_CR_ENABLE_DEVICE_MASK);
465 ret = xiic_clear_rx_fifo(i2c);
470 xiic_setreg32(i2c, XIIC_DGIER_OFFSET, XIIC_GINTR_ENABLE_MASK);
472 xiic_irq_clr_en(i2c, XIIC_INTR_ARB_LOST_MASK);
477 static void xiic_deinit(struct xiic_i2c *i2c)
481 xiic_setreg32(i2c, XIIC_RESETR_OFFSET, XIIC_RESET_MASK);
484 cr = xiic_getreg8(i2c, XIIC_CR_REG_OFFSET);
485 xiic_setreg8(i2c, XIIC_CR_REG_OFFSET, cr & ~XIIC_CR_ENABLE_DEVICE_MASK);
488 static void xiic_smbus_block_read_setup(struct xiic_i2c *i2c)
496 i2c->rx_msg->flags &= ~I2C_M_RECV_LEN;
499 i2c->smbus_block_read = true;
502 rxmsg_len = xiic_getreg8(i2c, XIIC_DRR_REG_OFFSET);
504 i2c->rx_msg->buf[i2c->rx_pos++] = rxmsg_len;
515 i2c->rx_msg->len = rxmsg_len + 1;
524 i2c->rx_msg->len = SMBUS_BLOCK_READ_MIN_LEN;
531 i2c->rx_msg->len = rxmsg_len + 1;
533 xiic_setreg8(i2c, XIIC_RFD_REG_OFFSET, rfd_set);
539 i2c->tx_msg->len = 3;
540 i2c->smbus_block_read = false;
541 dev_err(i2c->adap.dev.parent, "smbus_block_read Invalid msg length\n");
544 static void xiic_read_rx(struct xiic_i2c *i2c)
550 bytes_in_fifo = xiic_getreg8(i2c, XIIC_RFO_REG_OFFSET) + 1;
552 dev_dbg(i2c->adap.dev.parent,
554 __func__, bytes_in_fifo, xiic_rx_space(i2c),
555 xiic_getreg8(i2c, XIIC_SR_REG_OFFSET),
556 xiic_getreg8(i2c, XIIC_CR_REG_OFFSET));
558 if (bytes_in_fifo > xiic_rx_space(i2c))
559 bytes_in_fifo = xiic_rx_space(i2c);
563 if (!i2c->dynamic) {
564 bytes_rem = xiic_rx_space(i2c) - bytes_in_fifo;
567 if (i2c->rx_msg->flags & I2C_M_RECV_LEN) {
568 xiic_smbus_block_read_setup(i2c);
579 cr = xiic_getreg8(i2c, XIIC_CR_REG_OFFSET);
580 xiic_setreg8(i2c, XIIC_CR_REG_OFFSET, cr |
586 if (i2c->nmsgs == 1) {
587 cr = xiic_getreg8(i2c, XIIC_CR_REG_OFFSET);
588 xiic_setreg8(i2c, XIIC_CR_REG_OFFSET, cr &
593 cr = xiic_getreg8(i2c, XIIC_CR_REG_OFFSET);
594 xiic_setreg8(i2c, XIIC_CR_REG_OFFSET, cr &
601 i2c->rx_msg->buf[i2c->rx_pos++] =
602 xiic_getreg8(i2c, XIIC_DRR_REG_OFFSET);
605 if (i2c->dynamic) {
609 bytes = min_t(u8, xiic_rx_space(i2c), IIC_RX_FIFO_DEPTH);
611 xiic_setreg8(i2c, XIIC_RFD_REG_OFFSET, bytes);
615 static int xiic_tx_fifo_space(struct xiic_i2c *i2c)
618 return IIC_TX_FIFO_DEPTH - xiic_getreg8(i2c, XIIC_TFO_REG_OFFSET) - 1;
621 static void xiic_fill_tx_fifo(struct xiic_i2c *i2c)
623 u8 fifo_space = xiic_tx_fifo_space(i2c);
624 int len = xiic_tx_space(i2c);
628 dev_dbg(i2c->adap.dev.parent, "%s entry, len: %d, fifo space: %d\n",
632 u16 data = i2c->tx_msg->buf[i2c->tx_pos++];
634 if (!xiic_tx_space(i2c) && i2c->nmsgs == 1) {
636 if (i2c->dynamic) {
643 status = xiic_wait_tx_empty(i2c);
648 cr = xiic_getreg8(i2c, XIIC_CR_REG_OFFSET);
649 xiic_setreg8(i2c, XIIC_CR_REG_OFFSET, cr &
652 dev_dbg(i2c->adap.dev.parent, "%s TX STOP\n", __func__);
654 xiic_setreg16(i2c, XIIC_DTR_REG_OFFSET, data);
658 static void xiic_wakeup(struct xiic_i2c *i2c, enum xilinx_i2c_state code)
660 i2c->tx_msg = NULL;
661 i2c->rx_msg = NULL;
662 i2c->nmsgs = 0;
663 i2c->state = code;
664 complete(&i2c->completion);
669 struct xiic_i2c *i2c = dev_id;
682 mutex_lock(&i2c->lock);
683 isr = xiic_getreg32(i2c, XIIC_IISR_OFFSET);
684 ier = xiic_getreg32(i2c, XIIC_IIER_OFFSET);
687 dev_dbg(i2c->adap.dev.parent, "%s: IER: 0x%x, ISR: 0x%x, pend: 0x%x\n",
689 dev_dbg(i2c->adap.dev.parent, "%s: SR: 0x%x, msg: %p, nmsgs: %d\n",
690 __func__, xiic_getreg8(i2c, XIIC_SR_REG_OFFSET),
691 i2c->tx_msg, i2c->nmsgs);
692 dev_dbg(i2c->adap.dev.parent, "%s, ISR: 0x%x, CR: 0x%x\n",
693 __func__, xiic_getreg32(i2c, XIIC_IISR_OFFSET),
694 xiic_getreg8(i2c, XIIC_CR_REG_OFFSET));
706 dev_dbg(i2c->adap.dev.parent, "%s error\n", __func__);
712 ret = xiic_reinit(i2c);
714 dev_dbg(i2c->adap.dev.parent, "reinit failed\n");
716 if (i2c->rx_msg) {
720 if (i2c->tx_msg) {
731 if (!i2c->rx_msg) {
732 dev_dbg(i2c->adap.dev.parent,
734 xiic_clear_rx_fifo(i2c);
738 xiic_read_rx(i2c);
739 if (xiic_rx_space(i2c) == 0) {
741 i2c->rx_msg = NULL;
746 dev_dbg(i2c->adap.dev.parent,
748 __func__, i2c->nmsgs);
754 if (i2c->nmsgs > 1) {
755 i2c->nmsgs--;
756 i2c->tx_msg++;
757 dev_dbg(i2c->adap.dev.parent,
769 if (!i2c->tx_msg) {
770 dev_dbg(i2c->adap.dev.parent,
775 xiic_fill_tx_fifo(i2c);
778 if (!xiic_tx_space(i2c) && xiic_tx_fifo_space(i2c) >= 2) {
779 dev_dbg(i2c->adap.dev.parent,
781 __func__, i2c->nmsgs);
782 if (i2c->nmsgs > 1) {
783 i2c->nmsgs--;
784 i2c->tx_msg++;
787 xiic_irq_dis(i2c, XIIC_INTR_TX_HALF_MASK);
789 dev_dbg(i2c->adap.dev.parent,
793 } else if (!xiic_tx_space(i2c) && (i2c->nmsgs == 1))
797 xiic_irq_dis(i2c, XIIC_INTR_TX_HALF_MASK);
805 xiic_irq_dis(i2c, XIIC_INTR_BNB_MASK);
807 if (i2c->tx_msg && i2c->smbus_block_read) {
808 i2c->smbus_block_read = false;
810 i2c->tx_msg->len = 1;
813 if (!i2c->tx_msg)
818 if (i2c->nmsgs == 1 && !i2c->rx_msg &&
819 xiic_tx_space(i2c) == 0)
826 dev_dbg(i2c->adap.dev.parent, "%s clr: 0x%x\n", __func__, clr);
828 xiic_setreg32(i2c, XIIC_IISR_OFFSET, clr);
830 __xiic_start_xfer(i2c);
832 xiic_wakeup(i2c, wakeup_code);
836 mutex_unlock(&i2c->lock);
840 static int xiic_bus_busy(struct xiic_i2c *i2c)
842 u8 sr = xiic_getreg8(i2c, XIIC_SR_REG_OFFSET);
847 static int xiic_busy(struct xiic_i2c *i2c)
852 if (i2c->tx_msg || i2c->rx_msg)
857 * should ignore it, since bus will never be released and i2c will be
860 if (i2c->singlemaster) {
868 err = xiic_bus_busy(i2c);
871 err = xiic_bus_busy(i2c);
877 static void xiic_start_recv(struct xiic_i2c *i2c)
881 struct i2c_msg *msg = i2c->rx_msg = i2c->tx_msg;
883 dev_dbg(i2c->adap.dev.parent, "%s entry, ISR: 0x%x, CR: 0x%x\n",
884 __func__, xiic_getreg32(i2c, XIIC_IISR_OFFSET),
885 xiic_getreg8(i2c, XIIC_CR_REG_OFFSET));
888 xiic_irq_dis(i2c, XIIC_INTR_TX_HALF_MASK | XIIC_INTR_TX_EMPTY_MASK);
890 if (i2c->dynamic) {
895 xiic_irq_clr_en(i2c, XIIC_INTR_RX_FULL_MASK |
911 xiic_setreg8(i2c, XIIC_RFD_REG_OFFSET, bytes);
914 xiic_setreg16(i2c, XIIC_DTR_REG_OFFSET,
919 val = (i2c->nmsgs == 1) ? XIIC_TX_DYN_STOP_MASK : 0;
922 xiic_setreg16(i2c, XIIC_DTR_REG_OFFSET, val);
924 xiic_irq_clr_en(i2c, XIIC_INTR_BNB_MASK);
932 if (i2c->prev_msg_tx) {
935 status = xiic_wait_tx_empty(i2c);
940 cr = xiic_getreg8(i2c, XIIC_CR_REG_OFFSET);
950 if (!(i2c->rx_msg->flags & I2C_M_RECV_LEN)) {
962 xiic_setreg8(i2c, XIIC_CR_REG_OFFSET, (cr |
967 xiic_setreg8(i2c, XIIC_RFD_REG_OFFSET, rfd_set);
970 xiic_irq_clr_en(i2c, XIIC_INTR_RX_FULL_MASK |
974 xiic_setreg16(i2c, XIIC_DTR_REG_OFFSET,
979 xiic_setreg8(i2c, XIIC_CR_REG_OFFSET, (cr |
983 dev_dbg(i2c->adap.dev.parent, "%s end, ISR: 0x%x, CR: 0x%x\n",
984 __func__, xiic_getreg32(i2c, XIIC_IISR_OFFSET),
985 xiic_getreg8(i2c, XIIC_CR_REG_OFFSET));
988 if (i2c->nmsgs == 1)
990 xiic_irq_clr_en(i2c, XIIC_INTR_BNB_MASK);
993 i2c->tx_pos = msg->len;
996 xiic_setreg32(i2c, XIIC_DGIER_OFFSET, XIIC_GINTR_ENABLE_MASK);
998 i2c->prev_msg_tx = false;
1001 static void xiic_start_send(struct xiic_i2c *i2c)
1005 struct i2c_msg *msg = i2c->tx_msg;
1007 dev_dbg(i2c->adap.dev.parent, "%s entry, msg: %p, len: %d",
1009 dev_dbg(i2c->adap.dev.parent, "%s entry, ISR: 0x%x, CR: 0x%x\n",
1010 __func__, xiic_getreg32(i2c, XIIC_IISR_OFFSET),
1011 xiic_getreg8(i2c, XIIC_CR_REG_OFFSET));
1013 if (i2c->dynamic) {
1018 if (i2c->nmsgs == 1 && msg->len == 0)
1022 xiic_setreg16(i2c, XIIC_DTR_REG_OFFSET, data);
1025 xiic_irq_clr_en(i2c, XIIC_INTR_TX_EMPTY_MASK |
1028 ((i2c->nmsgs > 1 || xiic_tx_space(i2c)) ?
1031 xiic_fill_tx_fifo(i2c);
1039 if (i2c->prev_msg_tx) {
1042 status = xiic_wait_tx_empty(i2c);
1047 cr = xiic_getreg8(i2c, XIIC_CR_REG_OFFSET);
1050 xiic_setreg8(i2c, XIIC_CR_REG_OFFSET, (cr |
1058 xiic_setreg16(i2c, XIIC_DTR_REG_OFFSET, data);
1061 xiic_fill_tx_fifo(i2c);
1065 cr = xiic_getreg8(i2c, XIIC_CR_REG_OFFSET);
1066 xiic_setreg8(i2c, XIIC_CR_REG_OFFSET, cr |
1072 xiic_irq_clr_en(i2c, XIIC_INTR_TX_EMPTY_MASK |
1076 i2c->prev_msg_tx = true;
1079 static void __xiic_start_xfer(struct xiic_i2c *i2c)
1081 int fifo_space = xiic_tx_fifo_space(i2c);
1083 dev_dbg(i2c->adap.dev.parent, "%s entry, msg: %p, fifos space: %d\n",
1084 __func__, i2c->tx_msg, fifo_space);
1086 if (!i2c->tx_msg)
1089 i2c->rx_pos = 0;
1090 i2c->tx_pos = 0;
1091 i2c->state = STATE_START;
1092 if (i2c->tx_msg->flags & I2C_M_RD) {
1094 xiic_start_recv(i2c);
1096 xiic_start_send(i2c);
1100 static int xiic_start_xfer(struct xiic_i2c *i2c, struct i2c_msg *msgs, int num)
1105 mutex_lock(&i2c->lock);
1107 ret = xiic_busy(i2c);
1111 i2c->tx_msg = msgs;
1112 i2c->rx_msg = NULL;
1113 i2c->nmsgs = num;
1114 init_completion(&i2c->completion);
1117 i2c->dynamic = true;
1120 i2c->prev_msg_tx = false;
1131 for (count = 0; count < i2c->nmsgs; count++) {
1132 broken_read = (i2c->quirks & DYNAMIC_MODE_READ_BROKEN_BIT) &&
1133 (i2c->tx_msg[count].flags & I2C_M_RD);
1134 max_read_len = (i2c->tx_msg[count].flags & I2C_M_RD) &&
1135 (i2c->tx_msg[count].len > MAX_READ_LENGTH_DYNAMIC);
1136 smbus_blk_read = (i2c->tx_msg[count].flags & I2C_M_RECV_LEN);
1139 i2c->dynamic = false;
1144 ret = xiic_reinit(i2c);
1146 __xiic_start_xfer(i2c);
1149 mutex_unlock(&i2c->lock);
1156 struct xiic_i2c *i2c = i2c_get_adapdata(adap);
1160 xiic_getreg8(i2c, XIIC_SR_REG_OFFSET));
1162 err = pm_runtime_resume_and_get(i2c->dev);
1166 err = xiic_start_xfer(i2c, msgs, num);
1172 err = wait_for_completion_timeout(&i2c->completion, XIIC_XFER_TIMEOUT);
1173 mutex_lock(&i2c->lock);
1175 i2c->tx_msg = NULL;
1176 i2c->rx_msg = NULL;
1177 i2c->nmsgs = 0;
1180 err = (i2c->state == STATE_DONE) ? num : -EIO;
1182 mutex_unlock(&i2c->lock);
1185 pm_runtime_mark_last_busy(i2c->dev);
1186 pm_runtime_put_autosuspend(i2c->dev);
1221 struct xiic_i2c *i2c;
1229 i2c = devm_kzalloc(&pdev->dev, sizeof(*i2c), GFP_KERNEL);
1230 if (!i2c)
1237 i2c->quirks = data->quirks;
1240 i2c->base = devm_platform_get_and_ioremap_resource(pdev, 0, &res);
1241 if (IS_ERR(i2c->base))
1242 return PTR_ERR(i2c->base);
1251 platform_set_drvdata(pdev, i2c);
1252 i2c->adap = xiic_adapter;
1253 i2c_set_adapdata(&i2c->adap, i2c);
1254 i2c->adap.dev.parent = &pdev->dev;
1255 i2c->adap.dev.of_node = pdev->dev.of_node;
1256 snprintf(i2c->adap.name, sizeof(i2c->adap.name),
1259 mutex_init(&i2c->lock);
1261 i2c->clk = devm_clk_get_enabled(&pdev->dev, NULL);
1262 if (IS_ERR(i2c->clk))
1263 return dev_err_probe(&pdev->dev, PTR_ERR(i2c->clk),
1266 i2c->dev = &pdev->dev;
1267 pm_runtime_set_autosuspend_delay(i2c->dev, XIIC_PM_TIMEOUT);
1268 pm_runtime_use_autosuspend(i2c->dev);
1269 pm_runtime_set_active(i2c->dev);
1270 pm_runtime_enable(i2c->dev);
1273 i2c->input_clk = clk_get_rate(i2c->clk);
1275 &i2c->i2c_clk);
1277 if (ret || i2c->i2c_clk > I2C_MAX_FAST_MODE_PLUS_FREQ)
1278 i2c->i2c_clk = 0;
1282 pdev->name, i2c);
1289 i2c->singlemaster =
1297 i2c->endianness = LITTLE;
1298 xiic_setreg32(i2c, XIIC_CR_REG_OFFSET, XIIC_CR_TX_FIFO_RESET_MASK);
1300 sr = xiic_getreg32(i2c, XIIC_SR_REG_OFFSET);
1302 i2c->endianness = BIG;
1304 ret = xiic_reinit(i2c);
1310 /* add i2c adapter to i2c tree */
1311 ret = i2c_add_adapter(&i2c->adap);
1313 xiic_deinit(i2c);
1320 i2c_new_client_device(&i2c->adap, pdata->devices + i);
1324 (unsigned long)res->start, irq, i2c->i2c_clk);
1337 struct xiic_i2c *i2c = platform_get_drvdata(pdev);
1341 i2c_del_adapter(&i2c->adap);
1343 ret = pm_runtime_get_sync(i2c->dev);
1349 xiic_deinit(i2c);
1351 pm_runtime_put_sync(i2c->dev);
1359 struct xiic_i2c *i2c = dev_get_drvdata(dev);
1361 clk_disable(i2c->clk);
1368 struct xiic_i2c *i2c = dev_get_drvdata(dev);
1371 ret = clk_enable(i2c->clk);