i2c/busses/i2c-stm32f7.c

187  * @cr1: Control register 1
194 	u32 cr1;
883 	u32 cr1, cr2;
894 	cr1 = readl_relaxed(base + STM32F7_I2C_CR1);
923 	cr1 |= STM32F7_I2C_CR1_ERRIE | STM32F7_I2C_CR1_TCIE |
927 	cr1 &= ~(STM32F7_I2C_CR1_RXIE | STM32F7_I2C_CR1_TXIE |
947 			cr1 |= STM32F7_I2C_CR1_RXIE;
949 			cr1 |= STM32F7_I2C_CR1_TXIE;
952 			cr1 |= STM32F7_I2C_CR1_RXDMAEN;
954 			cr1 |= STM32F7_I2C_CR1_TXDMAEN;
958 		cr1 &= ~STM32F7_I2C_ALL_IRQ_MASK; /* Disable all interrupts */
966 	writel_relaxed(cr1, base + STM32F7_I2C_CR1);
977 	u32 cr1, cr2;
984 	cr1 = readl_relaxed(base + STM32F7_I2C_CR1);
1079 		cr1 |= STM32F7_I2C_CR1_PECEN;
1085 		cr1 &= ~STM32F7_I2C_CR1_PECEN;
1094 	cr1 |= STM32F7_I2C_CR1_ERRIE | STM32F7_I2C_CR1_TCIE |
1098 	cr1 &= ~(STM32F7_I2C_CR1_RXIE | STM32F7_I2C_CR1_TXIE |
1117 			cr1 |= STM32F7_I2C_CR1_RXIE;
1119 			cr1 |= STM32F7_I2C_CR1_TXIE;
1122 			cr1 |= STM32F7_I2C_CR1_RXDMAEN;
1124 			cr1 |= STM32F7_I2C_CR1_TXDMAEN;
1133 	writel_relaxed(cr1, base + STM32F7_I2C_CR1);
1143 	u32 cr1, cr2;
1147 	cr1 = readl_relaxed(base + STM32F7_I2C_CR1);
1171 	if (cr1 & STM32F7_I2C_CR1_PECEN) {
1183 	cr1 &= ~(STM32F7_I2C_CR1_RXIE | STM32F7_I2C_CR1_TXIE);
1184 	cr1 |= STM32F7_I2C_CR1_RXIE;
1191 	cr1 &= ~(STM32F7_I2C_CR1_RXIE | STM32F7_I2C_CR1_TXIE |
1211 		cr1 |= STM32F7_I2C_CR1_RXIE;
1213 		cr1 |= STM32F7_I2C_CR1_RXDMAEN;
1219 	writel_relaxed(cr1, base + STM32F7_I2C_CR1);
2428 	backup_regs->cr1 = readl_relaxed(i2c_dev->base + STM32F7_I2C_CR1);
2442 	u32 cr1;
2450 	cr1 = readl_relaxed(i2c_dev->base + STM32F7_I2C_CR1);
2451 	if (cr1 & STM32F7_I2C_CR1_PE)
2456 	writel_relaxed(backup_regs->cr1 & ~STM32F7_I2C_CR1_PE,
2458 	if (backup_regs->cr1 & STM32F7_I2C_CR1_PE)