Lines Matching refs:cci
108 struct cci;
116 struct cci *cci;
127 struct cci {
139 struct cci *cci = dev;
143 val = readl(cci->base + CCI_IRQ_STATUS_0);
144 writel(val, cci->base + CCI_IRQ_CLEAR_0);
145 writel(0x1, cci->base + CCI_IRQ_GLOBAL_CLEAR_CMD);
148 complete(&cci->master[0].irq_complete);
149 if (cci->master[1].master)
150 complete(&cci->master[1].irq_complete);
157 cci->master[0].status = 0;
158 complete(&cci->master[0].irq_complete);
165 cci->master[1].status = 0;
166 complete(&cci->master[1].irq_complete);
181 writel(reset, cci->base + CCI_RESET_CMD);
186 cci->master[0].status = -ENXIO;
188 cci->master[0].status = -EIO;
190 writel(CCI_HALT_REQ_I2C_M0_Q0Q1, cci->base + CCI_HALT_REQ);
197 cci->master[1].status = -ENXIO;
199 cci->master[1].status = -EIO;
201 writel(CCI_HALT_REQ_I2C_M1_Q0Q1, cci->base + CCI_HALT_REQ);
208 static int cci_halt(struct cci *cci, u8 master_num)
213 if (master_num >= cci->data->num_masters) {
214 dev_err(cci->dev, "Unsupported master idx (%u)\n", master_num);
219 master = &cci->master[master_num];
222 writel(val, cci->base + CCI_HALT_REQ);
225 dev_err(cci->dev, "CCI halt timeout\n");
232 static int cci_reset(struct cci *cci)
238 reinit_completion(&cci->master[0].irq_complete);
239 writel(CCI_RESET_CMD_MASK, cci->base + CCI_RESET_CMD);
241 if (!wait_for_completion_timeout(&cci->master[0].irq_complete,
243 dev_err(cci->dev, "CCI reset timeout\n");
250 static int cci_init(struct cci *cci)
265 writel(val, cci->base + CCI_IRQ_MASK_0);
267 for (i = 0; i < cci->data->num_masters; i++) {
268 int mode = cci->master[i].mode;
271 if (!cci->master[i].cci)
274 hw = &cci->data->params[mode];
277 writel(val, cci->base + CCI_I2C_Mm_SCL_CTL(i));
280 writel(val, cci->base + CCI_I2C_Mm_SDA_CTL_0(i));
283 writel(val, cci->base + CCI_I2C_Mm_SDA_CTL_1(i));
286 writel(val, cci->base + CCI_I2C_Mm_SDA_CTL_2(i));
289 writel(val, cci->base + CCI_I2C_Mm_MISC_CTL(i));
295 static int cci_run_queue(struct cci *cci, u8 master, u8 queue)
299 val = readl(cci->base + CCI_I2C_Mm_Qn_CUR_WORD_CNT(master, queue));
300 writel(val, cci->base + CCI_I2C_Mm_Qn_EXEC_WORD_CNT(master, queue));
302 reinit_completion(&cci->master[master].irq_complete);
304 writel(val, cci->base + CCI_QUEUE_START);
306 if (!wait_for_completion_timeout(&cci->master[master].irq_complete,
308 dev_err(cci->dev, "master %d queue %d timeout\n",
310 cci_reset(cci);
311 cci_init(cci);
315 return cci->master[master].status;
318 static int cci_validate_queue(struct cci *cci, u8 master, u8 queue)
322 val = readl(cci->base + CCI_I2C_Mm_Qn_CUR_WORD_CNT(master, queue));
323 if (val == cci->data->queue_size[queue])
330 writel(val, cci->base + CCI_I2C_Mm_Qn_LOAD_DATA(master, queue));
332 return cci_run_queue(cci, master, queue);
335 static int cci_i2c_read(struct cci *cci, u16 master,
347 ret = cci_validate_queue(cci, master, queue);
352 writel(val, cci->base + CCI_I2C_Mm_Qn_LOAD_DATA(master, queue));
355 writel(val, cci->base + CCI_I2C_Mm_Qn_LOAD_DATA(master, queue));
357 ret = cci_run_queue(cci, master, queue);
361 words_read = readl(cci->base + CCI_I2C_Mm_READ_BUF_LEVEL(master));
364 dev_err(cci->dev, "words read = %d, words expected = %d\n",
370 val = readl(cci->base + CCI_I2C_Mm_READ_DATA(master));
388 static int cci_i2c_write(struct cci *cci, u16 master,
400 ret = cci_validate_queue(cci, master, queue);
405 writel(val, cci->base + CCI_I2C_Mm_Qn_LOAD_DATA(master, queue));
417 writel(val, cci->base + CCI_I2C_Mm_Qn_LOAD_DATA(master, queue));
421 writel(val, cci->base + CCI_I2C_Mm_Qn_LOAD_DATA(master, queue));
423 return cci_run_queue(cci, master, queue);
429 struct cci *cci = cci_master->cci;
432 ret = pm_runtime_get_sync(cci->dev);
438 ret = cci_i2c_read(cci, cci_master->master,
442 ret = cci_i2c_write(cci, cci_master->master,
454 pm_runtime_mark_last_busy(cci->dev);
455 pm_runtime_put_autosuspend(cci->dev);
470 static int cci_enable_clocks(struct cci *cci)
472 return clk_bulk_prepare_enable(cci->nclocks, cci->clocks);
475 static void cci_disable_clocks(struct cci *cci)
477 clk_bulk_disable_unprepare(cci->nclocks, cci->clocks);
482 struct cci *cci = dev_get_drvdata(dev);
484 cci_disable_clocks(cci);
490 struct cci *cci = dev_get_drvdata(dev);
493 ret = cci_enable_clocks(cci);
497 cci_init(cci);
529 struct cci *cci;
533 cci = devm_kzalloc(dev, sizeof(*cci), GFP_KERNEL);
534 if (!cci)
537 cci->dev = dev;
538 platform_set_drvdata(pdev, cci);
539 cci->data = device_get_match_data(dev);
540 if (!cci->data)
553 if (idx >= cci->data->num_masters) {
555 child, idx, cci->data->num_masters - 1);
559 master = &cci->master[idx];
560 master->adap.quirks = &cci->data->quirks;
565 master->cci = cci;
584 cci->base = devm_platform_get_and_ioremap_resource(pdev, 0, &r);
585 if (IS_ERR(cci->base))
586 return PTR_ERR(cci->base);
590 ret = devm_clk_bulk_get_all(dev, &cci->clocks);
595 cci->nclocks = ret;
598 for (i = 0; i < cci->nclocks; i++) {
599 if (!strcmp(cci->clocks[i].id, "cci")) {
600 cci_clk_rate = clk_get_rate(cci->clocks[i].clk);
605 if (cci_clk_rate != cci->data->cci_clk_rate) {
606 /* cci clock set by the bootloader or via assigned clock rate
609 dev_warn(dev, "Found %lu cci clk rate while %lu was expected\n",
610 cci_clk_rate, cci->data->cci_clk_rate);
613 ret = cci_enable_clocks(cci);
622 cci->irq = ret;
624 ret = devm_request_irq(dev, cci->irq, cci_isr, 0, dev_name(dev), cci);
630 val = readl(cci->base + CCI_HW_VERSION);
633 ret = cci_reset(cci);
637 ret = cci_init(cci);
646 for (i = 0; i < cci->data->num_masters; i++) {
647 if (!cci->master[i].cci)
650 ret = i2c_add_adapter(&cci->master[i].adap);
652 of_node_put(cci->master[i].adap.dev.of_node);
664 if (cci->master[i].cci) {
665 i2c_del_adapter(&cci->master[i].adap);
666 of_node_put(cci->master[i].adap.dev.of_node);
670 disable_irq(cci->irq);
672 cci_disable_clocks(cci);
679 struct cci *cci = platform_get_drvdata(pdev);
682 for (i = 0; i < cci->data->num_masters; i++) {
683 if (cci->master[i].cci) {
684 i2c_del_adapter(&cci->master[i].adap);
685 of_node_put(cci->master[i].adap.dev.of_node);
687 cci_halt(cci, i);
690 disable_irq(cci->irq);
810 { .compatible = "qcom,msm8226-cci", .data = &cci_v1_data},
811 { .compatible = "qcom,msm8974-cci", .data = &cci_v1_5_data},
812 { .compatible = "qcom,msm8996-cci", .data = &cci_v2_data},
819 { .compatible = "qcom,msm8916-cci", .data = &cci_v1_data},
820 { .compatible = "qcom,sdm845-cci", .data = &cci_v2_data},
821 { .compatible = "qcom,sm8250-cci", .data = &cci_v2_data},
822 { .compatible = "qcom,sm8450-cci", .data = &cci_v2_data},
831 .name = "i2c-qcom-cci",