Lines Matching refs:drv_data
176 mv64xxx_i2c_prepare_for_io(struct mv64xxx_i2c_data *drv_data,
181 drv_data->cntl_bits = MV64XXX_I2C_REG_CONTROL_ACK |
184 if (!drv_data->atomic)
185 drv_data->cntl_bits |= MV64XXX_I2C_REG_CONTROL_INTEN;
191 drv_data->addr1 = 0xf0 | (((u32)msg->addr & 0x300) >> 7) | dir;
192 drv_data->addr2 = (u32)msg->addr & 0xff;
194 drv_data->addr1 = MV64XXX_I2C_ADDR_ADDR((u32)msg->addr) | dir;
195 drv_data->addr2 = 0;
209 mv64xxx_i2c_hw_init(struct mv64xxx_i2c_data *drv_data)
211 if (drv_data->offload_enabled) {
212 writel(0, drv_data->reg_base + MV64XXX_I2C_REG_BRIDGE_CONTROL);
213 writel(0, drv_data->reg_base + MV64XXX_I2C_REG_BRIDGE_TIMING);
214 writel(0, drv_data->reg_base +
216 writel(0, drv_data->reg_base +
220 writel(0, drv_data->reg_base + drv_data->reg_offsets.soft_reset);
221 writel(MV64XXX_I2C_BAUD_DIV_M(drv_data->freq_m) | MV64XXX_I2C_BAUD_DIV_N(drv_data->freq_n),
222 drv_data->reg_base + drv_data->reg_offsets.clock);
223 writel(0, drv_data->reg_base + drv_data->reg_offsets.addr);
224 writel(0, drv_data->reg_base + drv_data->reg_offsets.ext_addr);
226 drv_data->reg_base + drv_data->reg_offsets.control);
228 if (drv_data->errata_delay)
231 drv_data->state = MV64XXX_I2C_STATE_IDLE;
235 mv64xxx_i2c_fsm(struct mv64xxx_i2c_data *drv_data, u32 status)
242 if (drv_data->state == MV64XXX_I2C_STATE_IDLE) {
243 drv_data->action = MV64XXX_I2C_ACTION_SEND_STOP;
252 drv_data->action = MV64XXX_I2C_ACTION_SEND_ADDR_1;
253 drv_data->state = MV64XXX_I2C_STATE_WAITING_FOR_ADDR_1_ACK;
258 if (drv_data->msg->flags & I2C_M_TEN) {
259 drv_data->action = MV64XXX_I2C_ACTION_SEND_ADDR_2;
260 drv_data->state =
267 if ((drv_data->bytes_left == 0)
268 || (drv_data->aborting
269 && (drv_data->byte_posn != 0))) {
270 if (drv_data->send_stop || drv_data->aborting) {
271 drv_data->action = MV64XXX_I2C_ACTION_SEND_STOP;
272 drv_data->state = MV64XXX_I2C_STATE_IDLE;
274 drv_data->action =
276 drv_data->state =
280 drv_data->action = MV64XXX_I2C_ACTION_SEND_DATA;
281 drv_data->state =
283 drv_data->bytes_left--;
289 if (drv_data->msg->flags & I2C_M_TEN) {
290 drv_data->action = MV64XXX_I2C_ACTION_SEND_ADDR_2;
291 drv_data->state =
297 if (drv_data->bytes_left == 0) {
298 drv_data->action = MV64XXX_I2C_ACTION_SEND_STOP;
299 drv_data->state = MV64XXX_I2C_STATE_IDLE;
305 drv_data->action = MV64XXX_I2C_ACTION_CONTINUE;
307 drv_data->action = MV64XXX_I2C_ACTION_RCV_DATA;
308 drv_data->bytes_left--;
310 drv_data->state = MV64XXX_I2C_STATE_WAITING_FOR_SLAVE_DATA;
312 if ((drv_data->bytes_left == 1) || drv_data->aborting)
313 drv_data->cntl_bits &= ~MV64XXX_I2C_REG_CONTROL_ACK;
317 drv_data->action = MV64XXX_I2C_ACTION_RCV_DATA_STOP;
318 drv_data->state = MV64XXX_I2C_STATE_IDLE;
325 drv_data->action = MV64XXX_I2C_ACTION_SEND_STOP;
326 drv_data->state = MV64XXX_I2C_STATE_IDLE;
327 drv_data->rc = -ENXIO;
331 dev_err(&drv_data->adapter.dev,
334 drv_data->state, status, drv_data->msg->addr,
335 drv_data->msg->flags);
336 drv_data->action = MV64XXX_I2C_ACTION_SEND_STOP;
337 mv64xxx_i2c_hw_init(drv_data);
338 i2c_recover_bus(&drv_data->adapter);
339 drv_data->rc = -EAGAIN;
343 static void mv64xxx_i2c_send_start(struct mv64xxx_i2c_data *drv_data)
345 drv_data->msg = drv_data->msgs;
346 drv_data->byte_posn = 0;
347 drv_data->bytes_left = drv_data->msg->len;
348 drv_data->aborting = 0;
349 drv_data->rc = 0;
351 mv64xxx_i2c_prepare_for_io(drv_data, drv_data->msgs);
352 writel(drv_data->cntl_bits | MV64XXX_I2C_REG_CONTROL_START,
353 drv_data->reg_base + drv_data->reg_offsets.control);
357 mv64xxx_i2c_do_action(struct mv64xxx_i2c_data *drv_data)
359 switch(drv_data->action) {
362 BUG_ON(drv_data->num_msgs == 0);
364 drv_data->msgs++;
365 drv_data->num_msgs--;
366 mv64xxx_i2c_send_start(drv_data);
368 if (drv_data->errata_delay)
376 drv_data->send_stop = drv_data->num_msgs == 1;
380 writel(drv_data->cntl_bits,
381 drv_data->reg_base + drv_data->reg_offsets.control);
385 writel(drv_data->addr1,
386 drv_data->reg_base + drv_data->reg_offsets.data);
387 writel(drv_data->cntl_bits,
388 drv_data->reg_base + drv_data->reg_offsets.control);
392 writel(drv_data->addr2,
393 drv_data->reg_base + drv_data->reg_offsets.data);
394 writel(drv_data->cntl_bits,
395 drv_data->reg_base + drv_data->reg_offsets.control);
399 writel(drv_data->msg->buf[drv_data->byte_posn++],
400 drv_data->reg_base + drv_data->reg_offsets.data);
401 writel(drv_data->cntl_bits,
402 drv_data->reg_base + drv_data->reg_offsets.control);
406 drv_data->msg->buf[drv_data->byte_posn++] =
407 readl(drv_data->reg_base + drv_data->reg_offsets.data);
408 writel(drv_data->cntl_bits,
409 drv_data->reg_base + drv_data->reg_offsets.control);
413 drv_data->msg->buf[drv_data->byte_posn++] =
414 readl(drv_data->reg_base + drv_data->reg_offsets.data);
415 if (!drv_data->atomic)
416 drv_data->cntl_bits &= ~MV64XXX_I2C_REG_CONTROL_INTEN;
417 writel(drv_data->cntl_bits | MV64XXX_I2C_REG_CONTROL_STOP,
418 drv_data->reg_base + drv_data->reg_offsets.control);
419 drv_data->block = 0;
420 if (drv_data->errata_delay)
423 wake_up(&drv_data->waitq);
428 dev_err(&drv_data->adapter.dev,
430 drv_data->action);
431 drv_data->rc = -EIO;
434 if (!drv_data->atomic)
435 drv_data->cntl_bits &= ~MV64XXX_I2C_REG_CONTROL_INTEN;
436 writel(drv_data->cntl_bits | MV64XXX_I2C_REG_CONTROL_STOP,
437 drv_data->reg_base + drv_data->reg_offsets.control);
438 drv_data->block = 0;
439 wake_up(&drv_data->waitq);
445 mv64xxx_i2c_read_offload_rx_data(struct mv64xxx_i2c_data *drv_data,
450 buf[0] = readl(drv_data->reg_base + MV64XXX_I2C_REG_RX_DATA_LO);
451 buf[1] = readl(drv_data->reg_base + MV64XXX_I2C_REG_RX_DATA_HI);
457 mv64xxx_i2c_intr_offload(struct mv64xxx_i2c_data *drv_data)
461 cause = readl(drv_data->reg_base +
466 status = readl(drv_data->reg_base +
470 drv_data->rc = -EIO;
474 drv_data->rc = 0;
480 if (drv_data->num_msgs == 1 && drv_data->msgs[0].flags & I2C_M_RD) {
481 mv64xxx_i2c_read_offload_rx_data(drv_data, drv_data->msgs);
482 drv_data->msgs++;
483 drv_data->num_msgs--;
489 else if (drv_data->num_msgs == 2 &&
490 !(drv_data->msgs[0].flags & I2C_M_RD) &&
491 drv_data->msgs[1].flags & I2C_M_RD) {
492 mv64xxx_i2c_read_offload_rx_data(drv_data, drv_data->msgs + 1);
493 drv_data->msgs += 2;
494 drv_data->num_msgs -= 2;
498 writel(0, drv_data->reg_base + MV64XXX_I2C_REG_BRIDGE_CONTROL);
499 writel(0, drv_data->reg_base +
501 drv_data->block = 0;
503 wake_up(&drv_data->waitq);
511 struct mv64xxx_i2c_data *drv_data = dev_id;
515 spin_lock(&drv_data->lock);
517 if (drv_data->offload_enabled)
518 rc = mv64xxx_i2c_intr_offload(drv_data);
520 while (readl(drv_data->reg_base + drv_data->reg_offsets.control) &
530 if (drv_data->atomic)
533 status = readl(drv_data->reg_base + drv_data->reg_offsets.status);
534 mv64xxx_i2c_fsm(drv_data, status);
535 mv64xxx_i2c_do_action(drv_data);
537 if (drv_data->irq_clear_inverted)
538 writel(drv_data->cntl_bits | MV64XXX_I2C_REG_CONTROL_IFLG,
539 drv_data->reg_base + drv_data->reg_offsets.control);
543 spin_unlock(&drv_data->lock);
556 mv64xxx_i2c_wait_for_completion(struct mv64xxx_i2c_data *drv_data)
562 time_left = wait_event_timeout(drv_data->waitq,
563 !drv_data->block, drv_data->adapter.timeout);
565 spin_lock_irqsave(&drv_data->lock, flags);
567 drv_data->rc = -ETIMEDOUT;
570 drv_data->rc = time_left; /* errno value */
574 if (abort && drv_data->block) {
575 drv_data->aborting = 1;
576 spin_unlock_irqrestore(&drv_data->lock, flags);
578 time_left = wait_event_timeout(drv_data->waitq,
579 !drv_data->block, drv_data->adapter.timeout);
581 if ((time_left <= 0) && drv_data->block) {
582 drv_data->state = MV64XXX_I2C_STATE_IDLE;
583 dev_err(&drv_data->adapter.dev,
585 "time_left: %d\n", drv_data->block,
587 mv64xxx_i2c_hw_init(drv_data);
588 i2c_recover_bus(&drv_data->adapter);
591 spin_unlock_irqrestore(&drv_data->lock, flags);
594 static void mv64xxx_i2c_wait_polling(struct mv64xxx_i2c_data *drv_data)
596 ktime_t timeout = ktime_add_ms(ktime_get(), drv_data->adapter.timeout);
598 while (READ_ONCE(drv_data->block) &&
601 mv64xxx_i2c_intr(0, drv_data);
606 mv64xxx_i2c_execute_msg(struct mv64xxx_i2c_data *drv_data, struct i2c_msg *msg,
611 spin_lock_irqsave(&drv_data->lock, flags);
613 drv_data->state = MV64XXX_I2C_STATE_WAITING_FOR_START_COND;
615 drv_data->send_stop = is_last;
616 drv_data->block = 1;
617 mv64xxx_i2c_send_start(drv_data);
618 spin_unlock_irqrestore(&drv_data->lock, flags);
620 if (!drv_data->atomic)
621 mv64xxx_i2c_wait_for_completion(drv_data);
623 mv64xxx_i2c_wait_polling(drv_data);
625 return drv_data->rc;
629 mv64xxx_i2c_prepare_tx(struct mv64xxx_i2c_data *drv_data)
631 struct i2c_msg *msg = drv_data->msgs;
636 writel(buf[0], drv_data->reg_base + MV64XXX_I2C_REG_TX_DATA_LO);
637 writel(buf[1], drv_data->reg_base + MV64XXX_I2C_REG_TX_DATA_HI);
641 mv64xxx_i2c_offload_xfer(struct mv64xxx_i2c_data *drv_data)
643 struct i2c_msg *msgs = drv_data->msgs;
644 int num = drv_data->num_msgs;
648 spin_lock_irqsave(&drv_data->lock, flags);
663 mv64xxx_i2c_prepare_tx(drv_data);
686 mv64xxx_i2c_prepare_tx(drv_data);
690 drv_data->block = 1;
691 writel(ctrl_reg, drv_data->reg_base + MV64XXX_I2C_REG_BRIDGE_CONTROL);
692 spin_unlock_irqrestore(&drv_data->lock, flags);
694 mv64xxx_i2c_wait_for_completion(drv_data);
696 return drv_data->rc;
706 mv64xxx_i2c_can_offload(struct mv64xxx_i2c_data *drv_data)
708 struct i2c_msg *msgs = drv_data->msgs;
709 int num = drv_data->num_msgs;
711 if (!drv_data->offload_enabled)
753 struct mv64xxx_i2c_data *drv_data = i2c_get_adapdata(adap);
760 BUG_ON(drv_data->msgs != NULL);
761 drv_data->msgs = msgs;
762 drv_data->num_msgs = num;
764 if (mv64xxx_i2c_can_offload(drv_data) && !drv_data->atomic)
765 rc = mv64xxx_i2c_offload_xfer(drv_data);
767 rc = mv64xxx_i2c_execute_msg(drv_data, &msgs[0], num == 1);
772 drv_data->num_msgs = 0;
773 drv_data->msgs = NULL;
784 struct mv64xxx_i2c_data *drv_data = i2c_get_adapdata(adap);
786 drv_data->atomic = 0;
793 struct mv64xxx_i2c_data *drv_data = i2c_get_adapdata(adap);
795 drv_data->atomic = 1;
824 mv64xxx_calc_freq(struct mv64xxx_i2c_data *drv_data,
827 if (drv_data->clk_n_base_0)
834 mv64xxx_find_baud_factors(struct mv64xxx_i2c_data *drv_data,
842 freq = mv64xxx_calc_freq(drv_data, tclk, n, m);
845 drv_data->freq_m = m;
846 drv_data->freq_n = n;
858 mv64xxx_of_config(struct mv64xxx_i2c_data *drv_data,
870 if (!drv_data->clk) {
874 tclk = clk_get_rate(drv_data->clk);
881 drv_data->clk_n_base_0 = true;
883 if (!mv64xxx_find_baud_factors(drv_data, bus_freq, tclk)) {
888 drv_data->rstc = devm_reset_control_get_optional_exclusive(dev, NULL);
889 if (IS_ERR(drv_data->rstc)) {
890 rc = PTR_ERR(drv_data->rstc);
897 drv_data->adapter.timeout = HZ;
903 memcpy(&drv_data->reg_offsets, data, sizeof(drv_data->reg_offsets));
910 drv_data->offload_enabled = true;
913 drv_data->errata_delay = true;
917 drv_data->offload_enabled = false;
920 drv_data->errata_delay = true;
924 drv_data->irq_clear_inverted = true;
931 mv64xxx_of_config(struct mv64xxx_i2c_data *drv_data,
938 static int mv64xxx_i2c_init_recovery_info(struct mv64xxx_i2c_data *drv_data,
941 struct i2c_bus_recovery_info *rinfo = &drv_data->rinfo;
953 drv_data->adapter.bus_recovery_info = rinfo;
960 struct mv64xxx_i2c_data *drv_data = dev_get_drvdata(dev);
962 reset_control_assert(drv_data->rstc);
963 clk_disable_unprepare(drv_data->reg_clk);
964 clk_disable_unprepare(drv_data->clk);
972 struct mv64xxx_i2c_data *drv_data = dev_get_drvdata(dev);
974 clk_prepare_enable(drv_data->clk);
975 clk_prepare_enable(drv_data->reg_clk);
976 reset_control_reset(drv_data->rstc);
978 mv64xxx_i2c_hw_init(drv_data);
986 struct mv64xxx_i2c_data *drv_data;
993 drv_data = devm_kzalloc(&pd->dev, sizeof(struct mv64xxx_i2c_data),
995 if (!drv_data)
998 drv_data->reg_base = devm_platform_ioremap_resource(pd, 0);
999 if (IS_ERR(drv_data->reg_base))
1000 return PTR_ERR(drv_data->reg_base);
1002 strscpy(drv_data->adapter.name, MV64XXX_I2C_CTLR_NAME " adapter",
1003 sizeof(drv_data->adapter.name));
1005 init_waitqueue_head(&drv_data->waitq);
1006 spin_lock_init(&drv_data->lock);
1009 drv_data->clk = devm_clk_get(&pd->dev, NULL);
1010 if (IS_ERR(drv_data->clk)) {
1011 if (PTR_ERR(drv_data->clk) == -EPROBE_DEFER)
1013 drv_data->clk = NULL;
1016 drv_data->reg_clk = devm_clk_get(&pd->dev, "reg");
1017 if (IS_ERR(drv_data->reg_clk)) {
1018 if (PTR_ERR(drv_data->reg_clk) == -EPROBE_DEFER)
1020 drv_data->reg_clk = NULL;
1023 drv_data->irq = platform_get_irq(pd, 0);
1024 if (drv_data->irq < 0)
1025 return drv_data->irq;
1028 drv_data->freq_m = pdata->freq_m;
1029 drv_data->freq_n = pdata->freq_n;
1030 drv_data->adapter.timeout = msecs_to_jiffies(pdata->timeout);
1031 drv_data->offload_enabled = false;
1032 memcpy(&drv_data->reg_offsets, &mv64xxx_i2c_regs_mv64xxx, sizeof(drv_data->reg_offsets));
1034 rc = mv64xxx_of_config(drv_data, &pd->dev);
1039 rc = mv64xxx_i2c_init_recovery_info(drv_data, &pd->dev);
1043 drv_data->adapter.dev.parent = &pd->dev;
1044 drv_data->adapter.algo = &mv64xxx_i2c_algo;
1045 drv_data->adapter.owner = THIS_MODULE;
1046 drv_data->adapter.class = I2C_CLASS_DEPRECATED;
1047 drv_data->adapter.nr = pd->id;
1048 drv_data->adapter.dev.of_node = pd->dev.of_node;
1049 platform_set_drvdata(pd, drv_data);
1050 i2c_set_adapdata(&drv_data->adapter, drv_data);
1061 rc = request_irq(drv_data->irq, mv64xxx_i2c_intr, 0,
1062 MV64XXX_I2C_CTLR_NAME, drv_data);
1064 dev_err(&drv_data->adapter.dev,
1066 drv_data->irq, rc);
1068 } else if ((rc = i2c_add_numbered_adapter(&drv_data->adapter)) != 0) {
1069 dev_err(&drv_data->adapter.dev,
1077 free_irq(drv_data->irq, drv_data);
1089 struct mv64xxx_i2c_data *drv_data = platform_get_drvdata(pd);
1091 i2c_del_adapter(&drv_data->adapter);
1092 free_irq(drv_data->irq, drv_data);