i2c/busses/i2c-mchp-pci1xxxx.c

373 	u8 regval;
375 	regval = readb(p);
378 		regval |= SMBALERT_MST_PU;
380 		regval &= ~SMBALERT_MST_PU;
382 	writeb(regval, p);
388 	u8 regval;
390 	regval = readb(p);
393 		regval |= SMB_CORE_CMD_START;
395 		regval |= SMB_CORE_CMD_STOP;
397 	writeb(regval, p);
407 	u8 regval;
410 		regval = SMB_CORE_CTRL_FW_ACK | SMB_CORE_CTRL_ESO | SMB_CORE_CTRL_ACK;
412 		regval = SMB_CORE_CTRL_ESO | SMB_CORE_CTRL_ACK;
414 	writeb(regval, i2c->i2c_base + SMB_CORE_CTRL_REG_OFF);
442 	u8 regval;
444 	regval = readb(p);
445 	regval |= CTL_RESET_COUNTERS;
446 	writeb(regval, p);
452 	u8 regval;
454 	regval = readb(p);
456 		regval &= ~CTL_TRANSFER_DIR;
458 		regval |= CTL_TRANSFER_DIR;
460 	writeb(regval, p);
481 	u8 regval;
483 	regval = readb(p);
484 	regval |= CTL_RUN;
485 	writeb(regval, p);
491 	u8 regval;
493 	regval = readb(p);
494 	regval |= SMB_CORE_CMD_M_RUN;
495 	regval |= SMB_CORE_CMD_M_PROCEED;
496 	writeb(regval, p);
508 	u8 regval;
510 	regval = readb(p);
512 		regval |= SMB_CONFIG1_ASR;
514 		regval &= ~SMB_CONFIG1_ASR;
515 	writeb(regval, p);
562 	u8 regval;
564 	regval = readb(p);
566 		regval |= SMB_CORE_CMD_READM;
568 		regval &= ~SMB_CORE_CMD_READM;
570 	writeb(regval, p);
582 	u8 regval;
584 	regval = readb(p);
586 		regval &= ~intr_msk;
588 		regval |= intr_msk;
590 	writeb(regval, p);
597 	u8 regval;
599 	regval = readb(p1);
601 		regval |= I2C_INPUT_EN | I2C_OUTPUT_EN;
603 		regval &= ~(I2C_INPUT_EN | I2C_OUTPUT_EN);
605 	writeb(regval, p1);
607 	regval = readb(p2);
609 		regval |= I2C_INPUT_EN | I2C_OUTPUT_EN;
611 		regval &= ~(I2C_INPUT_EN | I2C_OUTPUT_EN);
613 	writeb(regval, p2);
619 	u8 regval;
621 	regval = readb(p);
623 		regval &= ~CTL_HOST_FIFO_ENTRY;
625 		regval |= CTL_HOST_FIFO_ENTRY;
627 	writeb(regval, p);
634 	u16 regval;
636 	regval = readw(p);
638 		regval &= ~intr_msk;
640 		regval |= intr_msk;
641 	writew(regval, p);
710 	u8 regval;
719 		regval = 0;
721 		regval = readl(p1);
725 	switch (regval) {
765 	u8 regval;
771 	regval = COMPLETION_MNAKX | COMPLETION_IDLE | COMPLETION_MDONE;
772 	writeb(regval, i2c->i2c_base + SMB_CORE_COMPLETION_REG_OFF3);
789 	u32 regval;
873 		regval = readb(p2);
876 		if (regval & COMPLETION_MNAKX) {
909 	u32 regval;
977 		regval = readb(p2);
978 		if (regval & COMPLETION_MNAKX) {
1071 	u32 regval;
1088 	regval = readl(p);
1089 	regval |= PERI_SMBUS_D3_RESET_DIS;
1090 	writel(regval, p);
1105 	u32 regval;
1107 	regval = readw(p1);
1108 	writew(regval, p1);
1110 	regval = readl(p2);
1111 	regval &= ~PERI_SMBUS_D3_RESET_DIS;
1112 	writel(regval, p2);