i2c/busses/i2c-hix5hd2.c

95 static u32 hix5hd2_i2c_clr_pend_irq(struct hix5hd2_i2c_priv *priv)
97 	u32 val = readl_relaxed(priv->regs + HIX5I2C_SR);
99 	writel_relaxed(val, priv->regs + HIX5I2C_ICR);
104 static void hix5hd2_i2c_clr_all_irq(struct hix5hd2_i2c_priv *priv)
106 	writel_relaxed(I2C_CLEAR_ALL, priv->regs + HIX5I2C_ICR);
109 static void hix5hd2_i2c_disable_irq(struct hix5hd2_i2c_priv *priv)
111 	writel_relaxed(0, priv->regs + HIX5I2C_CTRL);
114 static void hix5hd2_i2c_enable_irq(struct hix5hd2_i2c_priv *priv)
117 		       priv->regs + HIX5I2C_CTRL);
120 static void hix5hd2_i2c_drv_setrate(struct hix5hd2_i2c_priv *priv)
126 	val = readl_relaxed(priv->regs + HIX5I2C_CTRL);
127 	writel_relaxed(val & (~I2C_UNMASK_TOTAL), priv->regs + HIX5I2C_CTRL);
129 	rate = priv->freq;
130 	sysclock = clk_get_rate(priv->clk);
132 	writel_relaxed(scl, priv->regs + HIX5I2C_SCL_H);
133 	writel_relaxed(scl, priv->regs + HIX5I2C_SCL_L);
136 	writel_relaxed(val, priv->regs + HIX5I2C_CTRL);
138 	dev_dbg(priv->dev, "%s: sysclock=%d, rate=%d, scl=%d\n",
142 static void hix5hd2_i2c_init(struct hix5hd2_i2c_priv *priv)
144 	hix5hd2_i2c_disable_irq(priv);
145 	hix5hd2_i2c_drv_setrate(priv);
146 	hix5hd2_i2c_clr_all_irq(priv);
147 	hix5hd2_i2c_enable_irq(priv);
150 static void hix5hd2_i2c_reset(struct hix5hd2_i2c_priv *priv)
152 	clk_disable_unprepare(priv->clk);
154 	clk_prepare_enable(priv->clk);
155 	hix5hd2_i2c_init(priv);
158 static int hix5hd2_i2c_wait_bus_idle(struct hix5hd2_i2c_priv *priv)
166 		int_status = hix5hd2_i2c_clr_pend_irq(priv);
176 static void hix5hd2_rw_over(struct hix5hd2_i2c_priv *priv)
178 	if (priv->state == HIX5I2C_STAT_SND_STOP)
179 		dev_dbg(priv->dev, "%s: rw and send stop over\n", __func__);
181 		dev_dbg(priv->dev, "%s: have not data to send\n", __func__);
183 	priv->state = HIX5I2C_STAT_RW_SUCCESS;
184 	priv->err = 0;
187 static void hix5hd2_rw_handle_stop(struct hix5hd2_i2c_priv *priv)
189 	if (priv->stop) {
190 		priv->state = HIX5I2C_STAT_SND_STOP;
191 		writel_relaxed(I2C_STOP, priv->regs + HIX5I2C_COM);
193 		hix5hd2_rw_over(priv);
197 static void hix5hd2_read_handle(struct hix5hd2_i2c_priv *priv)
199 	if (priv->msg_len == 1) {
201 		writel_relaxed(I2C_READ | I2C_NO_ACK, priv->regs + HIX5I2C_COM);
202 	} else if (priv->msg_len > 1) {
204 		writel_relaxed(I2C_READ, priv->regs + HIX5I2C_COM);
206 		hix5hd2_rw_handle_stop(priv);
210 static void hix5hd2_write_handle(struct hix5hd2_i2c_priv *priv)
214 	if (priv->msg_len > 0) {
215 		data = priv->msg->buf[priv->msg_idx++];
216 		writel_relaxed(data, priv->regs + HIX5I2C_TXR);
217 		writel_relaxed(I2C_WRITE, priv->regs + HIX5I2C_COM);
219 		hix5hd2_rw_handle_stop(priv);
223 static int hix5hd2_rw_preprocess(struct hix5hd2_i2c_priv *priv)
227 	if (priv->state == HIX5I2C_STAT_INIT) {
228 		priv->state = HIX5I2C_STAT_RW;
229 	} else if (priv->state == HIX5I2C_STAT_RW) {
230 		if (priv->msg->flags & I2C_M_RD) {
231 			data = readl_relaxed(priv->regs + HIX5I2C_RXR);
232 			priv->msg->buf[priv->msg_idx++] = data;
234 		priv->msg_len--;
236 		dev_dbg(priv->dev, "%s: error: priv->state = %d, msg_len = %d\n",
237 			__func__, priv->state, priv->msg_len);
245 	struct hix5hd2_i2c_priv *priv = dev_id;
249 	spin_lock(&priv->lock);
251 	int_status = hix5hd2_i2c_clr_pend_irq(priv);
256 		dev_dbg(priv->dev, "ARB bus loss\n");
257 		priv->err = -EAGAIN;
258 		priv->state = HIX5I2C_STAT_RW_ERR;
262 		dev_dbg(priv->dev, "No ACK from device\n");
263 		priv->err = -ENXIO;
264 		priv->state = HIX5I2C_STAT_RW_ERR;
269 		if (priv->msg_len > 0) {
270 			ret = hix5hd2_rw_preprocess(priv);
272 				priv->err = ret;
273 				priv->state = HIX5I2C_STAT_RW_ERR;
276 			if (priv->msg->flags & I2C_M_RD)
277 				hix5hd2_read_handle(priv);
279 				hix5hd2_write_handle(priv);
281 			hix5hd2_rw_over(priv);
286 	if ((priv->state == HIX5I2C_STAT_RW_SUCCESS &&
287 	     priv->msg->len == priv->msg_idx) ||
288 	    (priv->state == HIX5I2C_STAT_RW_ERR)) {
289 		hix5hd2_i2c_disable_irq(priv);
290 		hix5hd2_i2c_clr_pend_irq(priv);
291 		complete(&priv->msg_complete);
294 	spin_unlock(&priv->lock);
299 static void hix5hd2_i2c_message_start(struct hix5hd2_i2c_priv *priv, int stop)
303 	spin_lock_irqsave(&priv->lock, flags);
304 	hix5hd2_i2c_clr_all_irq(priv);
305 	hix5hd2_i2c_enable_irq(priv);
307 	writel_relaxed(i2c_8bit_addr_from_msg(priv->msg),
308 		       priv->regs + HIX5I2C_TXR);
310 	writel_relaxed(I2C_WRITE | I2C_START, priv->regs + HIX5I2C_COM);
311 	spin_unlock_irqrestore(&priv->lock, flags);
314 static int hix5hd2_i2c_xfer_msg(struct hix5hd2_i2c_priv *priv,
320 	priv->msg = msgs;
321 	priv->msg_idx = 0;
322 	priv->msg_len = priv->msg->len;
323 	priv->stop = stop;
324 	priv->err = 0;
325 	priv->state = HIX5I2C_STAT_INIT;
327 	reinit_completion(&priv->msg_complete);
328 	hix5hd2_i2c_message_start(priv, stop);
330 	timeout = wait_for_completion_timeout(&priv->msg_complete,
331 					      priv->adap.timeout);
333 		priv->state = HIX5I2C_STAT_RW_ERR;
334 		priv->err = -ETIMEDOUT;
335 		dev_warn(priv->dev, "%s timeout=%d\n",
337 			 priv->adap.timeout);
339 	ret = priv->state;
345 	if (priv->state == HIX5I2C_STAT_RW_SUCCESS && stop)
346 		ret = hix5hd2_i2c_wait_bus_idle(priv);
349 		hix5hd2_i2c_reset(priv);
351 	return priv->err;
357 	struct hix5hd2_i2c_priv *priv = i2c_get_adapdata(adap);
360 	pm_runtime_get_sync(priv->dev);
368 		ret = hix5hd2_i2c_xfer_msg(priv, msgs, stop);
376 	pm_runtime_mark_last_busy(priv->dev);
377 	pm_runtime_put_autosuspend(priv->dev);
394 	struct hix5hd2_i2c_priv *priv;
398 	priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
399 	if (!priv)
404 		priv->freq = I2C_MAX_STANDARD_MODE_FREQ;
407 			priv->freq = I2C_MAX_FAST_MODE_FREQ;
408 			dev_warn(priv->dev, "use max freq %d instead\n",
411 			priv->freq = freq;
415 	priv->regs = devm_platform_ioremap_resource(pdev, 0);
416 	if (IS_ERR(priv->regs))
417 		return PTR_ERR(priv->regs);
423 	priv->clk = devm_clk_get_enabled(&pdev->dev, NULL);
424 	if (IS_ERR(priv->clk)) {
426 		return PTR_ERR(priv->clk);
429 	strscpy(priv->adap.name, "hix5hd2-i2c", sizeof(priv->adap.name));
430 	priv->dev = &pdev->dev;
431 	priv->adap.owner = THIS_MODULE;
432 	priv->adap.algo = &hix5hd2_i2c_algorithm;
433 	priv->adap.retries = 3;
434 	priv->adap.dev.of_node = np;
435 	priv->adap.algo_data = priv;
436 	priv->adap.dev.parent = &pdev->dev;
437 	i2c_set_adapdata(&priv->adap, priv);
438 	platform_set_drvdata(pdev, priv);
439 	spin_lock_init(&priv->lock);
440 	init_completion(&priv->msg_complete);
442 	hix5hd2_i2c_init(priv);
445 			       IRQF_NO_SUSPEND, dev_name(&pdev->dev), priv);
451 	pm_runtime_set_autosuspend_delay(priv->dev, MSEC_PER_SEC);
452 	pm_runtime_use_autosuspend(priv->dev);
453 	pm_runtime_set_active(priv->dev);
454 	pm_runtime_enable(priv->dev);
456 	ret = i2c_add_adapter(&priv->adap);
463 	pm_runtime_disable(priv->dev);
464 	pm_runtime_set_suspended(priv->dev);
471 	struct hix5hd2_i2c_priv *priv = platform_get_drvdata(pdev);
473 	i2c_del_adapter(&priv->adap);
474 	pm_runtime_disable(priv->dev);
475 	pm_runtime_set_suspended(priv->dev);
480 	struct hix5hd2_i2c_priv *priv = dev_get_drvdata(dev);
482 	clk_disable_unprepare(priv->clk);
489 	struct hix5hd2_i2c_priv *priv = dev_get_drvdata(dev);
491 	clk_prepare_enable(priv->clk);
492 	hix5hd2_i2c_init(priv);