i2c/busses/i2c-hisi.c

114 static void hisi_i2c_enable_int(struct hisi_i2c_controller *ctlr, u32 mask)
116 	writel_relaxed(mask, ctlr->iobase + HISI_I2C_INT_MASK);
119 static void hisi_i2c_disable_int(struct hisi_i2c_controller *ctlr, u32 mask)
121 	writel_relaxed((~mask) & HISI_I2C_INT_ALL, ctlr->iobase + HISI_I2C_INT_MASK);
124 static void hisi_i2c_clear_int(struct hisi_i2c_controller *ctlr, u32 mask)
126 	writel_relaxed(mask, ctlr->iobase + HISI_I2C_INT_CLR);
129 static void hisi_i2c_clear_tx_int(struct hisi_i2c_controller *ctlr, u32 mask)
131 	writel_relaxed(mask, ctlr->iobase + HISI_I2C_TX_INT_CLR);
134 static void hisi_i2c_handle_errors(struct hisi_i2c_controller *ctlr)
136 	u32 int_err = ctlr->xfer_err, reg;
139 		reg = readl(ctlr->iobase + HISI_I2C_FIFO_STATE);
142 			dev_err(ctlr->dev, "rx fifo error read\n");
145 			dev_err(ctlr->dev, "rx fifo error write\n");
148 			dev_err(ctlr->dev, "tx fifo error read\n");
151 			dev_err(ctlr->dev, "tx fifo error write\n");
155 static int hisi_i2c_start_xfer(struct hisi_i2c_controller *ctlr)
157 	struct i2c_msg *msg = ctlr->msgs;
160 	reg = readl(ctlr->iobase + HISI_I2C_FRAME_CTRL);
164 	writel(reg, ctlr->iobase + HISI_I2C_FRAME_CTRL);
166 	reg = readl(ctlr->iobase + HISI_I2C_SLV_ADDR);
169 	writel(reg, ctlr->iobase + HISI_I2C_SLV_ADDR);
171 	reg = readl(ctlr->iobase + HISI_I2C_FIFO_CTRL);
173 	writel(reg, ctlr->iobase + HISI_I2C_FIFO_CTRL);
175 	writel(reg, ctlr->iobase + HISI_I2C_FIFO_CTRL);
177 	hisi_i2c_clear_int(ctlr, HISI_I2C_INT_ALL);
178 	hisi_i2c_clear_tx_int(ctlr, HISI_I2C_TX_AEMPTY_INT);
179 	hisi_i2c_enable_int(ctlr, HISI_I2C_INT_ALL);
184 static void hisi_i2c_reset_xfer(struct hisi_i2c_controller *ctlr)
186 	ctlr->msg_num = 0;
187 	ctlr->xfer_err = 0;
188 	ctlr->msg_tx_idx = 0;
189 	ctlr->msg_rx_idx = 0;
190 	ctlr->buf_tx_idx = 0;
191 	ctlr->buf_rx_idx = 0;
203 	struct hisi_i2c_controller *ctlr = i2c_get_adapdata(adap);
207 	hisi_i2c_reset_xfer(ctlr);
208 	ctlr->completion = &done;
209 	ctlr->msg_num = num;
210 	ctlr->msgs = msgs;
212 	hisi_i2c_start_xfer(ctlr);
214 	if (!wait_for_completion_timeout(ctlr->completion, adap->timeout)) {
215 		hisi_i2c_disable_int(ctlr, HISI_I2C_INT_ALL);
216 		synchronize_irq(ctlr->irq);
217 		i2c_recover_bus(&ctlr->adapter);
218 		dev_err(ctlr->dev, "bus transfer timeout\n");
222 	if (ctlr->xfer_err) {
223 		hisi_i2c_handle_errors(ctlr);
227 	hisi_i2c_reset_xfer(ctlr);
228 	ctlr->completion = NULL;
243 static int hisi_i2c_read_rx_fifo(struct hisi_i2c_controller *ctlr)
248 	while (ctlr->msg_rx_idx < ctlr->msg_num) {
249 		cur_msg = ctlr->msgs + ctlr->msg_rx_idx;
252 			ctlr->msg_rx_idx++;
256 		fifo_state = readl(ctlr->iobase + HISI_I2C_FIFO_STATE);
258 		       ctlr->buf_rx_idx < cur_msg->len) {
259 			cur_msg->buf[ctlr->buf_rx_idx++] = readl(ctlr->iobase + HISI_I2C_RXDATA);
260 			fifo_state = readl(ctlr->iobase + HISI_I2C_FIFO_STATE);
263 		if (ctlr->buf_rx_idx == cur_msg->len) {
264 			ctlr->buf_rx_idx = 0;
265 			ctlr->msg_rx_idx++;
275 static void hisi_i2c_xfer_msg(struct hisi_i2c_controller *ctlr)
282 	while (ctlr->msg_tx_idx < ctlr->msg_num) {
283 		cur_msg = ctlr->msgs + ctlr->msg_tx_idx;
284 		last_msg = (ctlr->msg_tx_idx == ctlr->msg_num - 1);
287 		if (ctlr->msg_tx_idx && !ctlr->buf_tx_idx)
290 		fifo_state = readl(ctlr->iobase + HISI_I2C_FIFO_STATE);
292 		       ctlr->buf_tx_idx < cur_msg->len && max_write) {
301 			if (ctlr->buf_tx_idx == cur_msg->len - 1 && last_msg)
308 						  cur_msg->buf[ctlr->buf_tx_idx]);
310 			writel(cmd, ctlr->iobase + HISI_I2C_CMD_TXDATA);
311 			ctlr->buf_tx_idx++;
314 			fifo_state = readl(ctlr->iobase + HISI_I2C_FIFO_STATE);
318 		if (ctlr->buf_tx_idx == cur_msg->len) {
319 			ctlr->buf_tx_idx = 0;
320 			ctlr->msg_tx_idx++;
332 	if (ctlr->msg_tx_idx == ctlr->msg_num)
333 		hisi_i2c_disable_int(ctlr, HISI_I2C_INT_TX_EMPTY);
335 	hisi_i2c_clear_tx_int(ctlr, HISI_I2C_TX_AEMPTY_INT);
340 	struct hisi_i2c_controller *ctlr = context;
348 	if (!ctlr->completion)
351 	int_stat = readl(ctlr->iobase + HISI_I2C_INT_MSTAT);
352 	hisi_i2c_clear_int(ctlr, int_stat);
357 		hisi_i2c_xfer_msg(ctlr);
360 		ctlr->xfer_err = int_stat;
366 		hisi_i2c_read_rx_fifo(ctlr);
374 		hisi_i2c_disable_int(ctlr, HISI_I2C_INT_ALL);
375 		hisi_i2c_clear_int(ctlr, HISI_I2C_INT_ALL);
376 		hisi_i2c_clear_tx_int(ctlr, HISI_I2C_TX_AEMPTY_INT);
377 		complete(ctlr->completion);
389 static void hisi_i2c_set_scl(struct hisi_i2c_controller *ctlr,
397 	total_cnt = DIV_ROUND_UP_ULL(ctlr->clk_rate_khz * HZ_PER_KHZ, ctlr->t.bus_freq_hz);
403 	scl_fall_cnt = NSEC_TO_CYCLES(ctlr->t.scl_fall_ns, ctlr->clk_rate_khz);
405 	scl_rise_cnt = NSEC_TO_CYCLES(ctlr->t.scl_rise_ns, ctlr->clk_rate_khz);
408 	scl_hcnt = t_scl_hcnt - ctlr->spk_len - 7 - scl_fall_cnt;
411 	writel(scl_hcnt, ctlr->iobase + reg_hcnt);
412 	writel(scl_lcnt, ctlr->iobase + reg_lcnt);
415 static void hisi_i2c_configure_bus(struct hisi_i2c_controller *ctlr)
419 	i2c_parse_fw_timings(ctlr->dev, &ctlr->t, true);
420 	ctlr->spk_len = NSEC_TO_CYCLES(ctlr->t.digital_filter_width_ns, ctlr->clk_rate_khz);
422 	switch (ctlr->t.bus_freq_hz) {
425 		hisi_i2c_set_scl(ctlr, 26, 76, HISI_I2C_FS_SCL_HCNT, HISI_I2C_FS_SCL_LCNT);
429 		hisi_i2c_set_scl(ctlr, 6, 22, HISI_I2C_HS_SCL_HCNT, HISI_I2C_HS_SCL_LCNT);
436 		ctlr->t.bus_freq_hz = I2C_MAX_STANDARD_MODE_FREQ;
437 		hisi_i2c_set_scl(ctlr, 40, 87, HISI_I2C_SS_SCL_HCNT, HISI_I2C_SS_SCL_LCNT);
441 	reg = readl(ctlr->iobase + HISI_I2C_FRAME_CTRL);
444 	writel(reg, ctlr->iobase + HISI_I2C_FRAME_CTRL);
446 	sda_hold_cnt = NSEC_TO_CYCLES(ctlr->t.sda_hold_ns, ctlr->clk_rate_khz);
449 	writel(reg, ctlr->iobase + HISI_I2C_SDA_HOLD);
451 	writel(ctlr->spk_len, ctlr->iobase + HISI_I2C_FS_SPK_LEN);
455 	writel(reg, ctlr->iobase + HISI_I2C_FIFO_CTRL);
460 	struct hisi_i2c_controller *ctlr;
467 	ctlr = devm_kzalloc(dev, sizeof(*ctlr), GFP_KERNEL);
468 	if (!ctlr)
471 	ctlr->iobase = devm_platform_ioremap_resource(pdev, 0);
472 	if (IS_ERR(ctlr->iobase))
473 		return PTR_ERR(ctlr->iobase);
475 	ctlr->irq = platform_get_irq(pdev, 0);
476 	if (ctlr->irq < 0)
477 		return ctlr->irq;
479 	ctlr->dev = dev;
481 	hisi_i2c_disable_int(ctlr, HISI_I2C_INT_ALL);
483 	ret = devm_request_irq(dev, ctlr->irq, hisi_i2c_irq, 0, "hisi-i2c", ctlr);
487 	ctlr->clk = devm_clk_get_optional_enabled(&pdev->dev, NULL);
488 	if (IS_ERR_OR_NULL(ctlr->clk)) {
493 		clk_rate_hz = clk_get_rate(ctlr->clk);
496 	ctlr->clk_rate_khz = DIV_ROUND_UP_ULL(clk_rate_hz, HZ_PER_KHZ);
498 	hisi_i2c_configure_bus(ctlr);
500 	adapter = &ctlr->adapter;
506 	i2c_set_adapdata(adapter, ctlr);
512 	hw_version = readl(ctlr->iobase + HISI_I2C_VERSION);
513 	dev_info(ctlr->dev, "speed mode is %s. hw version 0x%x\n",
514 		 i2c_freq_mode_string(ctlr->t.bus_freq_hz), hw_version);