i2c/busses/i2c-designware-master.c

34 	regmap_write(dev->map, DW_IC_TX_TL, dev->tx_fifo_depth / 2);
35 	regmap_write(dev->map, DW_IC_RX_TL, 0);
38 	regmap_write(dev->map, DW_IC_CON, dev->master_cfg);
54 	ret = regmap_read(dev->map, DW_IC_COMP_PARAM_1, &comp_param1);
188 	regmap_write(dev->map, DW_IC_SS_SCL_HCNT, dev->ss_hcnt);
189 	regmap_write(dev->map, DW_IC_SS_SCL_LCNT, dev->ss_lcnt);
192 	regmap_write(dev->map, DW_IC_FS_SCL_HCNT, dev->fs_hcnt);
193 	regmap_write(dev->map, DW_IC_FS_SCL_LCNT, dev->fs_lcnt);
197 		regmap_write(dev->map, DW_IC_HS_SCL_HCNT, dev->hs_hcnt);
198 		regmap_write(dev->map, DW_IC_HS_SCL_LCNT, dev->hs_lcnt);
203 		regmap_write(dev->map, DW_IC_SDA_HOLD, dev->sda_hold_time);
232 	regmap_update_bits(dev->map, DW_IC_CON, DW_IC_CON_10BITADDR_MASTER,
239 	regmap_write(dev->map, DW_IC_TAR,
249 	regmap_read(dev->map, DW_IC_ENABLE_STATUS, &dummy);
252 	regmap_read(dev->map, DW_IC_CLR_INTR, &dummy);
261 	ret = regmap_read_poll_timeout(dev->map, DW_IC_INTR_STAT, val,
298 	regmap_write(dev->map, AMD_UCSI_INTR_REG, AMD_UCSI_INTR_EN);
310 			regmap_write(dev->map, DW_IC_TX_TL, buf_len - 1);
322 				regmap_write(dev->map, DW_IC_DATA_CMD, 0x100);
323 				regmap_write(dev->map, DW_IC_DATA_CMD, 0x100 | cmd);
325 					regmap_write(dev->map, DW_IC_TX_TL, 2 * (buf_len - 1));
326 					regmap_write(dev->map, DW_IC_RX_TL, 2 * (buf_len - 1));
337 						regmap_read(dev->map, DW_IC_DATA_CMD, &val);
345 				regmap_write(dev->map, DW_IC_DATA_CMD, *tx_buf++ | cmd);
406 		regmap_read(dev->map, DW_IC_TXFLR, &flr);
409 		regmap_read(dev->map, DW_IC_RXFLR, &flr);
443 				regmap_write(dev->map, DW_IC_DATA_CMD,
448 				regmap_write(dev->map, DW_IC_DATA_CMD,
538 		regmap_read(dev->map, DW_IC_RXFLR, &rx_valid);
543 			regmap_read(dev->map, DW_IC_DATA_CMD, &tmp);
592 		regmap_read(dev->map, DW_IC_INTR_STAT, &stat);
594 		regmap_read(dev->map, DW_IC_RAW_INTR_STAT, &stat);
606 		regmap_read(dev->map, DW_IC_CLR_RX_UNDER, &dummy);
608 		regmap_read(dev->map, DW_IC_CLR_RX_OVER, &dummy);
610 		regmap_read(dev->map, DW_IC_CLR_TX_OVER, &dummy);
612 		regmap_read(dev->map, DW_IC_CLR_RD_REQ, &dummy);
618 		regmap_read(dev->map, DW_IC_TX_ABRT_SOURCE, &dev->abort_source);
619 		regmap_read(dev->map, DW_IC_CLR_TX_ABRT, &dummy);
622 		regmap_read(dev->map, DW_IC_CLR_RX_DONE, &dummy);
624 		regmap_read(dev->map, DW_IC_CLR_ACTIVITY, &dummy);
627 		regmap_read(dev->map, DW_IC_CLR_STOP_DET, &dummy);
629 		regmap_read(dev->map, DW_IC_CLR_START_DET, &dummy);
631 		regmap_read(dev->map, DW_IC_CLR_GEN_CALL, &dummy);
684 	regmap_read(dev->map, DW_IC_ENABLE, &enabled);
685 	regmap_read(dev->map, DW_IC_RAW_INTR_STAT, &stat);
959 	ret = regmap_read(dev->map, DW_IC_CON, &ic_con);