i2c/busses/i2c-bcm-iproc.c

235 	u32 val;
242 		val = readl(iproc_i2c->base + offset);
245 		val = readl(iproc_i2c->base + offset);
248 	return val;
252 				    u32 offset, u32 val)
260 		writel(val, iproc_i2c->base + offset);
263 		writel(val, iproc_i2c->base + offset);
270 	u32 val;
275 		val = iproc_i2c_rd_reg(iproc_i2c, CFG_OFFSET);
276 		val |= BIT(CFG_RESET_SHIFT);
277 		iproc_i2c_wr_reg(iproc_i2c, CFG_OFFSET, val);
283 		val &= ~(BIT(CFG_RESET_SHIFT));
284 		iproc_i2c_wr_reg(iproc_i2c, CFG_OFFSET, val);
288 	val = (BIT(S_FIFO_RX_FLUSH_SHIFT) | BIT(S_FIFO_TX_FLUSH_SHIFT));
289 	iproc_i2c_wr_reg(iproc_i2c, S_FIFO_CTRL_OFFSET, val);
292 	val = iproc_i2c_rd_reg(iproc_i2c, TIM_CFG_OFFSET);
293 	val &= ~(TIM_RAND_SLAVE_STRETCH_MASK << TIM_RAND_SLAVE_STRETCH_SHIFT);
294 	val |= (SLAVE_CLOCK_STRETCH_TIME << TIM_RAND_SLAVE_STRETCH_SHIFT);
295 	iproc_i2c_wr_reg(iproc_i2c, TIM_CFG_OFFSET, val);
298 	val = iproc_i2c_rd_reg(iproc_i2c, S_CFG_SMBUS_ADDR_OFFSET);
299 	val |= BIT(S_CFG_EN_NIC_SMB_ADDR3_SHIFT);
300 	val &= ~(S_CFG_NIC_SMB_ADDR3_MASK << S_CFG_NIC_SMB_ADDR3_SHIFT);
301 	val |= (iproc_i2c->slave->addr << S_CFG_NIC_SMB_ADDR3_SHIFT);
302 	iproc_i2c_wr_reg(iproc_i2c, S_CFG_SMBUS_ADDR_OFFSET, val);
308 	val = BIT(IE_S_RX_EVENT_SHIFT);
310 	val |= BIT(IE_S_RX_FIFO_FULL_SHIFT);
312 	val |= BIT(IE_S_RD_EVENT_SHIFT);
314 	val |= BIT(IE_S_START_BUSY_SHIFT);
315 	iproc_i2c->slave_int_mask = val;
316 	iproc_i2c_wr_reg(iproc_i2c, IE_OFFSET, val);
322 	u32 val;
327 		val = iproc_i2c_rd_reg(iproc_i2c, S_CMD_OFFSET);
329 		if (!(val & BIT(S_CMD_START_BUSY_SHIFT))) {
330 			val = (val >> S_CMD_STATUS_SHIFT) & S_CMD_STATUS_MASK;
331 			if (val == S_CMD_STATUS_TIMEOUT ||
332 			    val == S_CMD_STATUS_MASTER_ABORT) {
334 					 (val == S_CMD_STATUS_TIMEOUT) ?
363 	u32 val;
366 		val = iproc_i2c_rd_reg(iproc_i2c, S_RX_OFFSET);
367 		rx_status = (val >> S_RX_STATUS_SHIFT) & S_RX_STATUS_MASK;
368 		rx_data = ((val >> S_RX_DATA_SHIFT) & S_RX_DATA_MASK);
438 	u32 val;
457 		val = BIT(S_CMD_START_BUSY_SHIFT);
458 		iproc_i2c_wr_reg(iproc_i2c, S_CMD_OFFSET, val);
472 		val = iproc_i2c_rd_reg(iproc_i2c, IE_OFFSET);
473 		val &= ~BIT(IE_S_TX_UNDERRUN_SHIFT);
474 		iproc_i2c_wr_reg(iproc_i2c, IE_OFFSET, val);
477 		val = BIT(S_TX_WR_STATUS_SHIFT);
478 		iproc_i2c_wr_reg(iproc_i2c, S_TX_OFFSET, val);
480 		val = BIT(S_CMD_START_BUSY_SHIFT);
481 		iproc_i2c_wr_reg(iproc_i2c, S_CMD_OFFSET, val);
484 		val = iproc_i2c_rd_reg(iproc_i2c, S_FIFO_CTRL_OFFSET);
485 		val |= (BIT(S_FIFO_TX_FLUSH_SHIFT));
486 		iproc_i2c_wr_reg(iproc_i2c, S_FIFO_CTRL_OFFSET, val);
518 		val = iproc_i2c_rd_reg(iproc_i2c, IE_OFFSET);
519 		val &= ~iproc_i2c->slave_int_mask;
520 		iproc_i2c_wr_reg(iproc_i2c, IE_OFFSET, val);
534 			val = BIT(IS_S_RX_FIFO_FULL_SHIFT);
535 			iproc_i2c_wr_reg(iproc_i2c, IS_OFFSET, val);
545 	uint32_t val;
549 		val = iproc_i2c_rd_reg(iproc_i2c, M_RX_OFFSET);
552 		if (!((val >> M_RX_STATUS_SHIFT) & M_RX_STATUS_MASK))
556 			(val >> M_RX_DATA_SHIFT) & M_RX_DATA_MASK;
566 	u32 val;
574 		val = msg->buf[idx];
578 			val |= BIT(M_TX_WR_STATUS_SHIFT);
595 		iproc_i2c_wr_reg(iproc_i2c, M_TX_OFFSET, val);
605 	u32 bytes_left, val;
612 			val = iproc_i2c_rd_reg(iproc_i2c, IE_OFFSET);
613 			val &= ~BIT(IS_M_RX_THLD_SHIFT);
614 			iproc_i2c_wr_reg(iproc_i2c, IE_OFFSET, val);
618 		val = iproc_i2c_rd_reg(iproc_i2c, M_FIFO_CTRL_OFFSET);
619 		val &= ~(M_FIFO_RX_THLD_MASK << M_FIFO_RX_THLD_SHIFT);
620 		val |= (bytes_left << M_FIFO_RX_THLD_SHIFT);
621 		iproc_i2c_wr_reg(iproc_i2c, M_FIFO_CTRL_OFFSET, val);
683 	u32 val;
686 	val = iproc_i2c_rd_reg(iproc_i2c, CFG_OFFSET);
687 	val |= BIT(CFG_RESET_SHIFT);
688 	val &= ~(BIT(CFG_EN_SHIFT));
689 	iproc_i2c_wr_reg(iproc_i2c, CFG_OFFSET, val);
695 	val &= ~(BIT(CFG_RESET_SHIFT));
696 	iproc_i2c_wr_reg(iproc_i2c, CFG_OFFSET, val);
699 	val = (BIT(M_FIFO_RX_FLUSH_SHIFT) | BIT(M_FIFO_TX_FLUSH_SHIFT));
700 	iproc_i2c_wr_reg(iproc_i2c, M_FIFO_CTRL_OFFSET, val);
702 	val = iproc_i2c_rd_reg(iproc_i2c, IE_OFFSET);
703 	val &= ~(IE_M_ALL_INTERRUPT_MASK <<
705 	iproc_i2c_wr_reg(iproc_i2c, IE_OFFSET, val);
716 	u32 val;
718 	val = iproc_i2c_rd_reg(iproc_i2c, CFG_OFFSET);
720 		val |= BIT(CFG_EN_SHIFT);
722 		val &= ~BIT(CFG_EN_SHIFT);
723 	iproc_i2c_wr_reg(iproc_i2c, CFG_OFFSET, val);
729 	u32 val;
731 	val = iproc_i2c_rd_reg(iproc_i2c, M_CMD_OFFSET);
732 	val = (val >> M_CMD_STATUS_SHIFT) & M_CMD_STATUS_MASK;
734 	switch (val) {
763 		dev_dbg(iproc_i2c->device, "unknown error code=%d\n", val);
779 	u32 val, status;
815 		val = BIT(M_FIFO_RX_FLUSH_SHIFT) | BIT(M_FIFO_TX_FLUSH_SHIFT);
816 		iproc_i2c_wr_reg(iproc_i2c, M_FIFO_CTRL_OFFSET, val);
823 		val = BIT(M_FIFO_RX_FLUSH_SHIFT) | BIT(M_FIFO_TX_FLUSH_SHIFT);
824 		iproc_i2c_wr_reg(iproc_i2c, M_FIFO_CTRL_OFFSET, val);
842 	u32 val, tmp, val_intr_en;
867 			val = msg->buf[i];
871 				val |= BIT(M_TX_WR_STATUS_SHIFT);
873 			iproc_i2c_wr_reg(iproc_i2c, M_TX_OFFSET, val);
889 		val = addr | BIT(M_TX_WR_STATUS_SHIFT);
890 		iproc_i2c_wr_reg(iproc_i2c, M_TX_OFFSET, val);
919 	val = BIT(M_CMD_START_BUSY_SHIFT);
923 		val |= (M_CMD_PROTOCOL_QUICK << M_CMD_PROTOCOL_SHIFT);
945 		val |= (protocol << M_CMD_PROTOCOL_SHIFT) |
948 		val |= (M_CMD_PROTOCOL_BLK_WR << M_CMD_PROTOCOL_SHIFT);
954 	return bcm_iproc_i2c_xfer_wait(iproc_i2c, msg, val);
984 	u32 val;
986 	val = I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
989 		val |= I2C_FUNC_SLAVE;
991 	return val;
1010 	u32 val;
1032 	val = iproc_i2c_rd_reg(iproc_i2c, TIM_CFG_OFFSET);
1033 	val &= ~BIT(TIM_CFG_MODE_400_SHIFT);
1034 	val |= (bus_speed == I2C_MAX_FAST_MODE_FREQ) << TIM_CFG_MODE_400_SHIFT;
1035 	iproc_i2c_wr_reg(iproc_i2c, TIM_CFG_OFFSET, val);
1166 	u32 val;
1177 	val = iproc_i2c_rd_reg(iproc_i2c, TIM_CFG_OFFSET);
1178 	val &= ~BIT(TIM_CFG_MODE_400_SHIFT);
1179 	val |= (iproc_i2c->bus_speed == I2C_MAX_FAST_MODE_FREQ) << TIM_CFG_MODE_400_SHIFT;
1180 	iproc_i2c_wr_reg(iproc_i2c, TIM_CFG_OFFSET, val);