Lines Matching refs:idev
154 static void i2c_int_disable(struct axxia_i2c_dev *idev, u32 mask)
158 int_en = readl(idev->base + MST_INT_ENABLE);
159 writel(int_en & ~mask, idev->base + MST_INT_ENABLE);
162 static void i2c_int_enable(struct axxia_i2c_dev *idev, u32 mask)
166 int_en = readl(idev->base + MST_INT_ENABLE);
167 writel(int_en | mask, idev->base + MST_INT_ENABLE);
178 static int axxia_i2c_init(struct axxia_i2c_dev *idev)
180 u32 divisor = clk_get_rate(idev->i2c_clk) / idev->bus_clk_rate;
181 u32 clk_mhz = clk_get_rate(idev->i2c_clk) / 1000000;
188 dev_dbg(idev->dev, "rate=%uHz per_clk=%uMHz -> ratio=1:%u\n",
189 idev->bus_clk_rate, clk_mhz, divisor);
192 writel(0x01, idev->base + SOFT_RESET);
194 while (readl(idev->base + SOFT_RESET) & 1) {
196 dev_warn(idev->dev, "Soft reset failed\n");
202 writel(0x1, idev->base + GLOBAL_CONTROL);
204 if (idev->bus_clk_rate <= I2C_MAX_STANDARD_MODE_FREQ) {
217 writel(t_high, idev->base + SCL_HIGH_PERIOD);
219 writel(t_low, idev->base + SCL_LOW_PERIOD);
221 writel(t_setup, idev->base + SDA_SETUP_TIME);
223 writel(ns_to_clk(300, clk_mhz), idev->base + SDA_HOLD_TIME);
225 writel(ns_to_clk(50, clk_mhz), idev->base + SPIKE_FLTR_LEN);
240 writel(prescale, idev->base + TIMER_CLOCK_DIV);
242 writel(WT_EN | WT_VALUE(tmo_clk), idev->base + WAIT_TIMER_CONTROL);
245 i2c_int_disable(idev, ~0);
248 writel(0x01, idev->base + INTERRUPT_ENABLE);
272 static int axxia_i2c_empty_rx_fifo(struct axxia_i2c_dev *idev)
274 struct i2c_msg *msg = idev->msg_r;
275 size_t rx_fifo_avail = readl(idev->base + MST_RX_FIFO);
276 int bytes_to_transfer = min(rx_fifo_avail, msg->len - idev->msg_xfrd_r);
279 int c = readl(idev->base + MST_DATA);
281 if (idev->msg_xfrd_r == 0 && i2c_m_recv_len(msg)) {
286 idev->msg_err = -EPROTO;
287 i2c_int_disable(idev, ~MST_STATUS_TSS);
288 complete(&idev->msg_complete);
292 writel(msg->len, idev->base + MST_RX_XFER);
294 msg->buf[idev->msg_xfrd_r++] = c;
304 static int axxia_i2c_fill_tx_fifo(struct axxia_i2c_dev *idev)
306 struct i2c_msg *msg = idev->msg;
307 size_t tx_fifo_avail = FIFO_SIZE - readl(idev->base + MST_TX_FIFO);
308 int bytes_to_transfer = min(tx_fifo_avail, msg->len - idev->msg_xfrd);
309 int ret = msg->len - idev->msg_xfrd - bytes_to_transfer;
312 writel(msg->buf[idev->msg_xfrd++], idev->base + MST_DATA);
317 static void axxia_i2c_slv_fifo_event(struct axxia_i2c_dev *idev)
319 u32 fifo_status = readl(idev->base + SLV_RX_FIFO);
322 dev_dbg(idev->dev, "slave irq fifo_status=0x%x\n", fifo_status);
326 i2c_slave_event(idev->slave,
329 val = readl(idev->base + SLV_DATA);
330 i2c_slave_event(idev->slave, I2C_SLAVE_WRITE_RECEIVED, &val);
333 readl(idev->base + SLV_DATA); /* dummy read */
334 i2c_slave_event(idev->slave, I2C_SLAVE_STOP, &val);
337 readl(idev->base + SLV_DATA); /* dummy read */
340 static irqreturn_t axxia_i2c_slv_isr(struct axxia_i2c_dev *idev)
342 u32 status = readl(idev->base + SLV_INT_STATUS);
345 dev_dbg(idev->dev, "slave irq status=0x%x\n", status);
348 axxia_i2c_slv_fifo_event(idev);
350 i2c_slave_event(idev->slave, I2C_SLAVE_READ_REQUESTED, &val);
351 writel(val, idev->base + SLV_DATA);
354 i2c_slave_event(idev->slave, I2C_SLAVE_READ_PROCESSED, &val);
355 writel(val, idev->base + SLV_DATA);
358 i2c_slave_event(idev->slave, I2C_SLAVE_STOP, &val);
360 writel(INT_SLV, idev->base + INTERRUPT_STATUS);
366 struct axxia_i2c_dev *idev = _dev;
370 status = readl(idev->base + INTERRUPT_STATUS);
373 ret = axxia_i2c_slv_isr(idev);
378 status = readl(idev->base + MST_INT_STATUS);
380 if (!idev->msg) {
381 dev_warn(idev->dev, "unexpected interrupt\n");
386 if (i2c_m_rd(idev->msg_r) && (status & MST_STATUS_RFL))
387 axxia_i2c_empty_rx_fifo(idev);
390 if (!i2c_m_rd(idev->msg) && (status & MST_STATUS_TFL)) {
391 if (axxia_i2c_fill_tx_fifo(idev) == 0)
392 i2c_int_disable(idev, MST_STATUS_TFL);
397 i2c_int_disable(idev, ~0);
399 idev->msg_err = -EAGAIN;
401 idev->msg_err = -ENXIO;
403 idev->msg_err = -EIO;
404 dev_dbg(idev->dev, "error %#x, addr=%#x rx=%u/%u tx=%u/%u\n",
406 idev->msg->addr,
407 readl(idev->base + MST_RX_BYTES_XFRD),
408 readl(idev->base + MST_RX_XFER),
409 readl(idev->base + MST_TX_BYTES_XFRD),
410 readl(idev->base + MST_TX_XFER));
411 complete(&idev->msg_complete);
414 i2c_int_disable(idev, ~MST_STATUS_TSS);
415 complete(&idev->msg_complete);
418 int mask = idev->last ? ~0 : ~MST_STATUS_TSS;
420 i2c_int_disable(idev, mask);
421 if (i2c_m_rd(idev->msg_r) && idev->msg_xfrd_r < idev->msg_r->len)
422 axxia_i2c_empty_rx_fifo(idev);
423 complete(&idev->msg_complete);
426 idev->msg_err = -ETIMEDOUT;
427 i2c_int_disable(idev, ~MST_STATUS_TSS);
428 complete(&idev->msg_complete);
433 writel(INT_MST, idev->base + INTERRUPT_STATUS);
438 static void axxia_i2c_set_addr(struct axxia_i2c_dev *idev, struct i2c_msg *msg)
460 writel(addr_1, idev->base + MST_ADDR_1);
461 writel(addr_2, idev->base + MST_ADDR_2);
468 static int axxia_i2c_handle_seq_nak(struct axxia_i2c_dev *idev)
473 if ((readl(idev->base + MST_COMMAND) & CMD_BUSY) == 0)
481 static int axxia_i2c_xfer_seq(struct axxia_i2c_dev *idev, struct i2c_msg msgs[])
487 axxia_i2c_set_addr(idev, &msgs[0]);
489 writel(msgs[0].len, idev->base + MST_TX_XFER);
490 writel(rlen, idev->base + MST_RX_XFER);
492 idev->msg = &msgs[0];
493 idev->msg_r = &msgs[1];
494 idev->msg_xfrd = 0;
495 idev->msg_xfrd_r = 0;
496 idev->last = true;
497 axxia_i2c_fill_tx_fifo(idev);
499 writel(CMD_SEQUENCE, idev->base + MST_COMMAND);
501 reinit_completion(&idev->msg_complete);
502 i2c_int_enable(idev, int_mask);
504 time_left = wait_for_completion_timeout(&idev->msg_complete,
507 if (idev->msg_err == -ENXIO) {
508 if (axxia_i2c_handle_seq_nak(idev))
509 axxia_i2c_init(idev);
510 } else if (readl(idev->base + MST_COMMAND) & CMD_BUSY) {
511 dev_warn(idev->dev, "busy after xfer\n");
515 idev->msg_err = -ETIMEDOUT;
516 i2c_recover_bus(&idev->adapter);
517 axxia_i2c_init(idev);
520 if (unlikely(idev->msg_err) && idev->msg_err != -ENXIO)
521 axxia_i2c_init(idev);
523 return idev->msg_err;
526 static int axxia_i2c_xfer_msg(struct axxia_i2c_dev *idev, struct i2c_msg *msg,
534 idev->msg = msg;
535 idev->msg_r = msg;
536 idev->msg_xfrd = 0;
537 idev->msg_xfrd_r = 0;
538 idev->last = last;
539 reinit_completion(&idev->msg_complete);
541 axxia_i2c_set_addr(idev, msg);
553 writel(rx_xfer, idev->base + MST_RX_XFER);
554 writel(tx_xfer, idev->base + MST_TX_XFER);
558 else if (axxia_i2c_fill_tx_fifo(idev) != 0)
561 wt_value = WT_VALUE(readl(idev->base + WAIT_TIMER_CONTROL));
563 writel(wt_value, idev->base + WAIT_TIMER_CONTROL);
565 if (idev->msg_err)
569 writel(CMD_MANUAL, idev->base + MST_COMMAND);
572 writel(CMD_AUTO, idev->base + MST_COMMAND);
576 writel(WT_EN | wt_value, idev->base + WAIT_TIMER_CONTROL);
578 i2c_int_enable(idev, int_mask);
580 time_left = wait_for_completion_timeout(&idev->msg_complete,
583 i2c_int_disable(idev, int_mask);
585 if (readl(idev->base + MST_COMMAND) & CMD_BUSY)
586 dev_warn(idev->dev, "busy after xfer\n");
589 idev->msg_err = -ETIMEDOUT;
590 i2c_recover_bus(&idev->adapter);
591 axxia_i2c_init(idev);
595 if (unlikely(idev->msg_err) && idev->msg_err != -ENXIO &&
596 idev->msg_err != -ETIMEDOUT)
597 axxia_i2c_init(idev);
599 return idev->msg_err;
617 struct axxia_i2c_dev *idev = i2c_get_adapdata(adap);
621 idev->msg_err = 0;
624 ret = axxia_i2c_xfer_seq(idev, msgs);
628 i2c_int_enable(idev, MST_STATUS_TSS);
631 ret = axxia_i2c_xfer_msg(idev, &msgs[i], i == (num - 1));
638 struct axxia_i2c_dev *idev = i2c_get_adapdata(adap);
640 return !!(readl(idev->base + I2C_BUS_MONITOR) & BM_SCLS);
645 struct axxia_i2c_dev *idev = i2c_get_adapdata(adap);
649 tmp = readl(idev->base + I2C_BUS_MONITOR) & BM_SDAC;
652 writel(tmp, idev->base + I2C_BUS_MONITOR);
657 struct axxia_i2c_dev *idev = i2c_get_adapdata(adap);
659 return !!(readl(idev->base + I2C_BUS_MONITOR) & BM_SDAS);
678 struct axxia_i2c_dev *idev = i2c_get_adapdata(slave->adapter);
682 if (idev->slave)
685 idev->slave = slave;
688 writel(GLOBAL_MST_EN | GLOBAL_SLV_EN, idev->base + GLOBAL_CONTROL);
689 writel(INT_MST | INT_SLV, idev->base + INTERRUPT_ENABLE);
696 writel(SLV_RX_ACSA1, idev->base + SLV_RX_CTL);
697 writel(dec_ctl, idev->base + SLV_ADDR_DEC_CTL);
698 writel(slave->addr, idev->base + SLV_ADDR_1);
703 writel(slv_int_mask, idev->base + SLV_INT_ENABLE);
710 struct axxia_i2c_dev *idev = i2c_get_adapdata(slave->adapter);
713 writel(GLOBAL_MST_EN, idev->base + GLOBAL_CONTROL);
714 writel(INT_MST, idev->base + INTERRUPT_ENABLE);
716 synchronize_irq(idev->irq);
718 idev->slave = NULL;
738 struct axxia_i2c_dev *idev = NULL;
742 idev = devm_kzalloc(&pdev->dev, sizeof(*idev), GFP_KERNEL);
743 if (!idev)
750 idev->irq = platform_get_irq(pdev, 0);
751 if (idev->irq < 0)
752 return idev->irq;
754 idev->i2c_clk = devm_clk_get(&pdev->dev, "i2c");
755 if (IS_ERR(idev->i2c_clk)) {
757 return PTR_ERR(idev->i2c_clk);
760 idev->base = base;
761 idev->dev = &pdev->dev;
762 init_completion(&idev->msg_complete);
764 of_property_read_u32(np, "clock-frequency", &idev->bus_clk_rate);
765 if (idev->bus_clk_rate == 0)
766 idev->bus_clk_rate = I2C_MAX_STANDARD_MODE_FREQ; /* default clock rate */
768 ret = clk_prepare_enable(idev->i2c_clk);
774 ret = axxia_i2c_init(idev);
780 ret = devm_request_irq(&pdev->dev, idev->irq, axxia_i2c_isr, 0,
781 pdev->name, idev);
783 dev_err(&pdev->dev, "failed to claim IRQ%d\n", idev->irq);
787 i2c_set_adapdata(&idev->adapter, idev);
788 strscpy(idev->adapter.name, pdev->name, sizeof(idev->adapter.name));
789 idev->adapter.owner = THIS_MODULE;
790 idev->adapter.algo = &axxia_i2c_algo;
791 idev->adapter.bus_recovery_info = &axxia_i2c_recovery_info;
792 idev->adapter.quirks = &axxia_i2c_quirks;
793 idev->adapter.dev.parent = &pdev->dev;
794 idev->adapter.dev.of_node = pdev->dev.of_node;
796 platform_set_drvdata(pdev, idev);
798 ret = i2c_add_adapter(&idev->adapter);
805 clk_disable_unprepare(idev->i2c_clk);
811 struct axxia_i2c_dev *idev = platform_get_drvdata(pdev);
813 clk_disable_unprepare(idev->i2c_clk);
814 i2c_del_adapter(&idev->adapter);