drivers/hwmon/nct7904.c

147 	int ret;
152 	ret = i2c_smbus_write_byte_data(data->client, BANK_SEL_REG, bank);
153 	if (ret == 0)
157 	return ret;
170 	int ret;
172 	ret = nct7904_bank_lock(data, bank);
173 	if (ret == 0)
174 		ret = i2c_smbus_read_byte_data(client, reg);
177 	return ret;
188 	int ret, hi;
190 	ret = nct7904_bank_lock(data, bank);
191 	if (ret == 0) {
192 		ret = i2c_smbus_read_byte_data(client, reg);
193 		if (ret >= 0) {
194 			hi = ret;
195 			ret = i2c_smbus_read_byte_data(client, reg + 1);
196 			if (ret >= 0)
197 				ret |= hi << 8;
202 	return ret;
210 	int ret;
212 	ret = nct7904_bank_lock(data, bank);
213 	if (ret == 0)
214 		ret = i2c_smbus_write_byte_data(client, reg, val);
217 	return ret;
225 	int ret;
229 		ret = nct7904_read_reg16(data, BANK_0,
231 		if (ret < 0)
232 			return ret;
233 		cnt = ((ret & 0xff00) >> 3) | (ret & 0x1f);
241 		ret = nct7904_read_reg16(data, BANK_1,
243 		if (ret < 0)
244 			return ret;
245 		cnt = ((ret & 0xff00) >> 3) | (ret & 0x1f);
253 		ret = nct7904_read_reg(data, BANK_0,
255 		if (ret < 0)
256 			return ret;
258 			data->fan_alarm[channel >> 3] = ret & 0xff;
261 			data->fan_alarm[channel >> 3] |= (ret & 0xff);
303 	int ret, volt, index;
309 		ret = nct7904_read_reg16(data, BANK_0,
311 		if (ret < 0)
312 			return ret;
313 		volt = ((ret & 0xff00) >> 5) | (ret & 0x7);
321 		ret = nct7904_read_reg16(data, BANK_1,
323 		if (ret < 0)
324 			return ret;
325 		volt = ((ret & 0xff00) >> 5) | (ret & 0x7);
333 		ret = nct7904_read_reg16(data, BANK_1,
335 		if (ret < 0)
336 			return ret;
337 		volt = ((ret & 0xff00) >> 5) | (ret & 0x7);
345 		ret = nct7904_read_reg(data, BANK_0,
347 		if (ret < 0)
348 			return ret;
350 			data->vsen_alarm[index >> 3] = ret & 0xff;
353 			data->vsen_alarm[index >> 3] |= (ret & 0xff);
391 	int ret, temp;
398 			ret = nct7904_read_reg16(data, BANK_0, LTD_HV_REG);
400 			ret = nct7904_read_reg16(data, BANK_0,
403 			ret = nct7904_read_reg16(data, BANK_0,
406 		if (ret < 0)
407 			return ret;
408 		temp = ((ret & 0xff00) >> 5) | (ret & 0x7);
413 			ret = nct7904_read_reg(data, BANK_0,
415 			if (ret < 0)
416 				return ret;
417 			*val = (ret >> 1) & 1;
419 			ret = nct7904_read_reg(data, BANK_0,
421 			if (ret < 0)
422 				return ret;
423 			*val = (ret >> (((channel * 2) + 1) & 0x07)) & 1;
426 				ret = nct7904_read_reg(data, BANK_0,
429 				if (ret < 0)
430 					return ret;
431 				*val = (ret >> ((channel - 5) & 0x07)) & 1;
433 				ret = nct7904_read_reg(data, BANK_0,
436 				if (ret < 0)
437 					return ret;
438 				*val = (ret >> (((channel - 5) & 0x07) - 4))
489 		ret = nct7904_read_reg(data, BANK_1, reg1);
491 		ret = nct7904_read_reg(data, BANK_1,
494 		ret = nct7904_read_reg(data, BANK_1,
497 	if (ret < 0)
498 		return ret;
499 	temps = ret;
543 	int ret;
547 		ret = nct7904_read_reg(data, BANK_3, FANCTL1_OUT_REG + channel);
548 		if (ret < 0)
549 			return ret;
550 		*val = ret;
553 		ret = nct7904_read_reg(data, BANK_3, FANCTL1_FMR_REG + channel);
554 		if (ret < 0)
555 			return ret;
557 		*val = ret ? 2 : 1;
568 	int ret;
598 		ret = nct7904_write_reg(data, BANK_1, reg1, val);
600 		ret = nct7904_write_reg(data, BANK_1,
603 		ret = nct7904_write_reg(data, BANK_1,
606 	return ret;
613 	int ret;
623 		ret = nct7904_write_reg(data, BANK_1,
625 		if (ret < 0)
626 			return ret;
628 		ret = nct7904_write_reg(data, BANK_1,
630 		return ret;
640 	int ret, index, tmp;
659 		ret = nct7904_write_reg(data, BANK_1,
661 		if (ret < 0)
662 			return ret;
668 		ret = nct7904_write_reg(data, BANK_1,
670 		return ret;
678 		ret = nct7904_write_reg(data, BANK_1,
680 		if (ret < 0)
681 			return ret;
687 		ret = nct7904_write_reg(data, BANK_1,
689 		return ret;
699 	int ret;
705 		ret = nct7904_write_reg(data, BANK_3, FANCTL1_OUT_REG + channel,
707 		return ret;
712 		ret = nct7904_write_reg(data, BANK_3, FANCTL1_FMR_REG + channel,
714 		return ret;
969 	int ret;
972 	ret = nct7904_write_reg(data, BANK_0, WDT_LOCK_REG, WDT_SOFT_DIS);
973 	if (ret < 0)
974 		return ret;
977 	ret = nct7904_write_reg(data, BANK_0, WDT_TIMER_REG, wdt->timeout / 60);
978 	if (ret < 0)
979 		return ret;
988 	int ret;
990 	ret = nct7904_read_reg(data, BANK_0, WDT_TIMER_REG);
991 	if (ret < 0)
994 	return ret * 60;
1017 	int ret, i;
1031 	ret = nct7904_read_reg16(data, BANK_0, FANIN_CTRL0_REG);
1032 	if (ret < 0)
1033 		return ret;
1034 	data->fanin_mask = (ret >> 8) | ((ret & 0xff) << 8);
1044 	ret = nct7904_read_reg16(data, BANK_0, VT_ADC_CTRL0_REG);
1045 	if (ret >= 0)
1046 		mask = (ret >> 8) | ((ret & 0xff) << 8);
1047 	ret = nct7904_read_reg(data, BANK_0, VT_ADC_CTRL2_REG);
1048 	if (ret >= 0)
1049 		mask |= (ret << 16);
1053 	ret = nct7904_read_reg(data, BANK_0, VT_ADC_CTRL0_REG);
1054 	if (ret < 0)
1055 		return ret;
1057 	if ((ret & 0x6) == 0x6)
1059 	if ((ret & 0x18) == 0x18)
1061 	if ((ret & 0x20) == 0x20)
1063 	if ((ret & 0x80) == 0x80)
1067 	ret = nct7904_read_reg(data, BANK_0, VT_ADC_CTRL2_REG);
1068 	if (ret < 0)
1069 		return ret;
1070 	if ((ret & 0x02) == 0x02)
1074 	ret = nct7904_read_reg(data, BANK_0, VT_ADC_MD_REG);
1075 	if (ret < 0)
1076 		return ret;
1080 		val = (ret >> (i * 2)) & 0x03;
1097 	ret = nct7904_read_reg(data, BANK_2, PFE_REG);
1098 	if (ret < 0)
1099 		return ret;
1100 	if (ret & 0x80) {
1103 		ret = nct7904_read_reg(data, BANK_2, TSI_CTRL_REG);
1104 		if (ret < 0)
1105 			return ret;
1106 		if (ret & 0x80)
1112 		ret = nct7904_read_reg(data, BANK_0, DTS_T_CTRL0_REG);
1113 		if (ret < 0)
1114 			return ret;
1115 		data->has_dts = ret & 0xF;
1117 			ret = nct7904_read_reg(data, BANK_0, DTS_T_CTRL1_REG);
1118 			if (ret < 0)
1119 				return ret;
1120 			data->has_dts |= (ret & 0xF) << 4;
1125 		ret = nct7904_read_reg(data, BANK_3, FANCTL1_FMR_REG + i);
1126 		if (ret < 0)
1127 			return ret;
1128 		data->fan_mode[i] = ret;
1133 		ret = nct7904_read_reg(data, BANK_0, SMI_STS1_REG + i);
1134 		if (ret < 0)
1135 			return ret;
1141 	ret = PTR_ERR_OR_ZERO(hwmon_dev);
1142 	if (ret)
1143 		return ret;