gpu/ipu-v3/ipu-pre.c

118 	struct ipu_pre *pre;
121 	list_for_each_entry(pre, &ipu_pre_list, list) {
122 		if (pre_node == pre->dev->of_node) {
124 			device_link_add(dev, pre->dev,
127 			return pre;
137 int ipu_pre_get(struct ipu_pre *pre)
141 	if (pre->in_use)
145 	writel(0, pre->regs + IPU_PRE_CTRL);
152 	writel(val, pre->regs + IPU_PRE_CTRL);
154 	pre->in_use = true;
158 void ipu_pre_put(struct ipu_pre *pre)
160 	writel(IPU_PRE_CTRL_SFTRST, pre->regs + IPU_PRE_CTRL);
162 	pre->in_use = false;
165 void ipu_pre_configure(struct ipu_pre *pre, unsigned int width,
175 		pre->safe_window_end = height - 2;
177 		pre->safe_window_end = DIV_ROUND_UP(height, 4) - 1;
179 	writel(bufaddr, pre->regs + IPU_PRE_CUR_BUF);
180 	writel(bufaddr, pre->regs + IPU_PRE_NEXT_BUF);
181 	pre->last_bufaddr = bufaddr;
188 	writel(val, pre->regs + IPU_PRE_PREFETCH_ENG_CTRL);
192 	writel(val, pre->regs + IPU_PRE_PREFETCH_ENG_INPUT_SIZE);
195 	writel(val, pre->regs + IPU_PRE_PREFETCH_ENG_PITCH);
200 	writel(val, pre->regs + IPU_PRE_STORE_ENG_CTRL);
204 	writel(val, pre->regs + IPU_PRE_STORE_ENG_SIZE);
207 	writel(val, pre->regs + IPU_PRE_STORE_ENG_PITCH);
209 	writel(pre->buffer_paddr, pre->regs + IPU_PRE_STORE_ENG_ADDR);
211 	val = readl(pre->regs + IPU_PRE_TPR_CTRL);
221 	writel(val, pre->regs + IPU_PRE_TPR_CTRL);
223 	val = readl(pre->regs + IPU_PRE_CTRL);
230 	writel(val, pre->regs + IPU_PRE_CTRL);
233 void ipu_pre_update(struct ipu_pre *pre, unsigned int bufaddr)
239 	if (bufaddr == pre->last_bufaddr)
242 	writel(bufaddr, pre->regs + IPU_PRE_NEXT_BUF);
243 	pre->last_bufaddr = bufaddr;
247 			dev_warn(pre->dev, "timeout waiting for PRE safe window\n");
251 		val = readl(pre->regs + IPU_PRE_STORE_ENG_STATUS);
255 	} while (current_yblock == 0 || current_yblock >= pre->safe_window_end);
257 	writel(IPU_PRE_CTRL_SDW_UPDATE, pre->regs + IPU_PRE_CTRL_SET);
260 bool ipu_pre_update_pending(struct ipu_pre *pre)
262 	return !!(readl_relaxed(pre->regs + IPU_PRE_CTRL) &
266 u32 ipu_pre_get_baddr(struct ipu_pre *pre)
268 	return (u32)pre->buffer_paddr;
274 	struct ipu_pre *pre;
276 	pre = devm_kzalloc(dev, sizeof(*pre), GFP_KERNEL);
277 	if (!pre)
280 	pre->regs = devm_platform_ioremap_resource(pdev, 0);
281 	if (IS_ERR(pre->regs))
282 		return PTR_ERR(pre->regs);
284 	pre->clk_axi = devm_clk_get(dev, "axi");
285 	if (IS_ERR(pre->clk_axi))
286 		return PTR_ERR(pre->clk_axi);
288 	pre->iram = of_gen_pool_get(dev->of_node, "fsl,iram", 0);
289 	if (!pre->iram)
297 	pre->buffer_virt = gen_pool_dma_alloc(pre->iram, IPU_PRE_MAX_WIDTH *
299 					      &pre->buffer_paddr);
300 	if (!pre->buffer_virt)
303 	clk_prepare_enable(pre->clk_axi);
305 	pre->dev = dev;
306 	platform_set_drvdata(pdev, pre);
308 	list_add(&pre->list, &ipu_pre_list);
317 	struct ipu_pre *pre = platform_get_drvdata(pdev);
320 	list_del(&pre->list);
324 	clk_disable_unprepare(pre->clk_axi);
326 	if (pre->buffer_virt)
327 		gen_pool_free(pre->iram, (unsigned long)pre->buffer_virt,
333 	{ .compatible = "fsl,imx6qp-pre", },
341 		.name	= "imx-ipu-pre",