gpu/ipu-v3/ipu-csi.c

177 static inline u32 ipu_csi_read(struct ipu_csi *csi, unsigned offset)
179 	return readl(csi->base + offset);
182 static inline void ipu_csi_write(struct ipu_csi *csi, u32 value,
185 	writel(value, csi->base + offset);
192 static int ipu_csi_set_testgen_mclk(struct ipu_csi *csi, u32 pixel_clk,
201 		dev_err(csi->ipu->dev,
206 	temp = ipu_csi_read(csi, CSI_SENS_CONF);
208 	ipu_csi_write(csi, temp | (div_ratio << CSI_SENS_CONF_DIVRATIO_SHIFT),
399 ipu_csi_set_bt_interlaced_codes(struct ipu_csi *csi,
430 		ipu_csi_write(csi, 0x40596 | CSI_CCIR_ERR_DET_EN,
432 		ipu_csi_write(csi, 0xD07DF, CSI_CCIR_CODE_2);
434 		dev_dbg(csi->ipu->dev, "capture field swap\n");
437 		ipu_csi_write(csi, 0xD07DF | CSI_CCIR_ERR_DET_EN,
439 		ipu_csi_write(csi, 0x40596, CSI_CCIR_CODE_2);
442 	ipu_csi_write(csi, 0xFF0000, CSI_CCIR_CODE_3);
448 int ipu_csi_init_interface(struct ipu_csi *csi,
482 	spin_lock_irqsave(&csi->lock, flags);
484 	ipu_csi_write(csi, data, CSI_SENS_CONF);
490 		ipu_csi_write(csi, 0x40030, CSI_CCIR_CODE_1);
491 		ipu_csi_write(csi, 0xFF0000, CSI_CCIR_CODE_3);
501 			dev_err(csi->ipu->dev,
507 		ret = ipu_csi_set_bt_interlaced_codes(csi, infmt, outfmt, std);
515 		ipu_csi_write(csi, 0x40030 | CSI_CCIR_ERR_DET_EN,
517 		ipu_csi_write(csi, 0xFF0000, CSI_CCIR_CODE_3);
521 		ipu_csi_write(csi, 0, CSI_CCIR_CODE_1);
526 	ipu_csi_write(csi, (width - 1) | ((height - 1) << 16),
529 	dev_dbg(csi->ipu->dev, "CSI_SENS_CONF = 0x%08X\n",
530 		ipu_csi_read(csi, CSI_SENS_CONF));
531 	dev_dbg(csi->ipu->dev, "CSI_ACT_FRM_SIZE = 0x%08X\n",
532 		ipu_csi_read(csi, CSI_ACT_FRM_SIZE));
535 	spin_unlock_irqrestore(&csi->lock, flags);
541 bool ipu_csi_is_interlaced(struct ipu_csi *csi)
546 	spin_lock_irqsave(&csi->lock, flags);
548 		(ipu_csi_read(csi, CSI_SENS_CONF) &
551 	spin_unlock_irqrestore(&csi->lock, flags);
565 		dev_err(csi->ipu->dev,
566 			"CSI %d sensor protocol unsupported\n", csi->id);
572 void ipu_csi_get_window(struct ipu_csi *csi, struct v4l2_rect *w)
577 	spin_lock_irqsave(&csi->lock, flags);
579 	reg = ipu_csi_read(csi, CSI_ACT_FRM_SIZE);
583 	reg = ipu_csi_read(csi, CSI_OUT_FRM_CTRL);
587 	spin_unlock_irqrestore(&csi->lock, flags);
591 void ipu_csi_set_window(struct ipu_csi *csi, struct v4l2_rect *w)
596 	spin_lock_irqsave(&csi->lock, flags);
598 	ipu_csi_write(csi, (w->width - 1) | ((w->height - 1) << 16),
601 	reg = ipu_csi_read(csi, CSI_OUT_FRM_CTRL);
604 	ipu_csi_write(csi, reg, CSI_OUT_FRM_CTRL);
606 	spin_unlock_irqrestore(&csi->lock, flags);
610 void ipu_csi_set_downsize(struct ipu_csi *csi, bool horiz, bool vert)
615 	spin_lock_irqsave(&csi->lock, flags);
617 	reg = ipu_csi_read(csi, CSI_OUT_FRM_CTRL);
621 	ipu_csi_write(csi, reg, CSI_OUT_FRM_CTRL);
623 	spin_unlock_irqrestore(&csi->lock, flags);
627 void ipu_csi_set_test_generator(struct ipu_csi *csi, bool active,
632 	u32 ipu_clk = clk_get_rate(csi->clk_ipu);
635 	spin_lock_irqsave(&csi->lock, flags);
637 	temp = ipu_csi_read(csi, CSI_TST_CTRL);
641 		ipu_csi_write(csi, temp, CSI_TST_CTRL);
644 		ipu_csi_set_testgen_mclk(csi, pix_clk, ipu_clk);
652 		ipu_csi_write(csi, temp, CSI_TST_CTRL);
655 	spin_unlock_irqrestore(&csi->lock, flags);
659 int ipu_csi_set_mipi_datatype(struct ipu_csi *csi, u32 vc,
674 	spin_lock_irqsave(&csi->lock, flags);
676 	temp = ipu_csi_read(csi, CSI_MIPI_DI);
679 	ipu_csi_write(csi, temp, CSI_MIPI_DI);
681 	spin_unlock_irqrestore(&csi->lock, flags);
687 int ipu_csi_set_skip_smfc(struct ipu_csi *csi, u32 skip,
696 	spin_lock_irqsave(&csi->lock, flags);
698 	temp = ipu_csi_read(csi, CSI_SKIP);
704 	ipu_csi_write(csi, temp, CSI_SKIP);
706 	spin_unlock_irqrestore(&csi->lock, flags);
712 int ipu_csi_set_dest(struct ipu_csi *csi, enum ipu_csi_dest csi_dest)
722 	spin_lock_irqsave(&csi->lock, flags);
724 	csi_sens_conf = ipu_csi_read(csi, CSI_SENS_CONF);
727 	ipu_csi_write(csi, csi_sens_conf, CSI_SENS_CONF);
729 	spin_unlock_irqrestore(&csi->lock, flags);
735 int ipu_csi_enable(struct ipu_csi *csi)
737 	ipu_module_enable(csi->ipu, csi->module);
743 int ipu_csi_disable(struct ipu_csi *csi)
745 	ipu_module_disable(csi->ipu, csi->module);
754 	struct ipu_csi *csi, *ret;
759 	csi = ipu->csi_priv[id];
760 	ret = csi;
762 	spin_lock_irqsave(&csi->lock, flags);
764 	if (csi->inuse) {
769 	csi->inuse = true;
771 	spin_unlock_irqrestore(&csi->lock, flags);
776 void ipu_csi_put(struct ipu_csi *csi)
780 	spin_lock_irqsave(&csi->lock, flags);
781 	csi->inuse = false;
782 	spin_unlock_irqrestore(&csi->lock, flags);
789 	struct ipu_csi *csi;
794 	csi = devm_kzalloc(dev, sizeof(*csi), GFP_KERNEL);
795 	if (!csi)
798 	ipu->csi_priv[id] = csi;
800 	spin_lock_init(&csi->lock);
801 	csi->module = module;
802 	csi->id = id;
803 	csi->clk_ipu = clk_ipu;
804 	csi->base = devm_ioremap(dev, base, PAGE_SIZE);
805 	if (!csi->base)
809 		id, base, csi->base);
810 	csi->ipu = ipu;
819 void ipu_csi_dump(struct ipu_csi *csi)
821 	dev_dbg(csi->ipu->dev, "CSI_SENS_CONF:     %08x\n",
822 		ipu_csi_read(csi, CSI_SENS_CONF));
823 	dev_dbg(csi->ipu->dev, "CSI_SENS_FRM_SIZE: %08x\n",
824 		ipu_csi_read(csi, CSI_SENS_FRM_SIZE));
825 	dev_dbg(csi->ipu->dev, "CSI_ACT_FRM_SIZE:  %08x\n",
826 		ipu_csi_read(csi, CSI_ACT_FRM_SIZE));
827 	dev_dbg(csi->ipu->dev, "CSI_OUT_FRM_CTRL:  %08x\n",
828 		ipu_csi_read(csi, CSI_OUT_FRM_CTRL));
829 	dev_dbg(csi->ipu->dev, "CSI_TST_CTRL:      %08x\n",
830 		ipu_csi_read(csi, CSI_TST_CTRL));
831 	dev_dbg(csi->ipu->dev, "CSI_CCIR_CODE_1:   %08x\n",
832 		ipu_csi_read(csi, CSI_CCIR_CODE_1));
833 	dev_dbg(csi->ipu->dev, "CSI_CCIR_CODE_2:   %08x\n",
834 		ipu_csi_read(csi, CSI_CCIR_CODE_2));
835 	dev_dbg(csi->ipu->dev, "CSI_CCIR_CODE_3:   %08x\n",
836 		ipu_csi_read(csi, CSI_CCIR_CODE_3));
837 	dev_dbg(csi->ipu->dev, "CSI_MIPI_DI:       %08x\n",
838 		ipu_csi_read(csi, CSI_MIPI_DI));
839 	dev_dbg(csi->ipu->dev, "CSI_SKIP:          %08x\n",
840 		ipu_csi_read(csi, CSI_SKIP));