gpu/ipu-v3/ipu-common.c

889 	const struct ipu_devtype *devtype = ipu->devtype;
891 	ret = ipu_cpmem_init(ipu, dev, ipu_base + devtype->cpmem_ofs);
897 	ret = ipu_csi_init(ipu, dev, 0, ipu_base + devtype->csi0_ofs,
904 	ret = ipu_csi_init(ipu, dev, 1, ipu_base + devtype->csi1_ofs,
912 			  ipu_base + devtype->ic_ofs,
913 			  ipu_base + devtype->tpm_ofs);
919 	ret = ipu_vdi_init(ipu, dev, ipu_base + devtype->vdi_ofs,
933 	ret = ipu_di_init(ipu, dev, 0, ipu_base + devtype->disp0_ofs,
940 	ret = ipu_di_init(ipu, dev, 1, ipu_base + devtype->disp1_ofs,
947 	ret = ipu_dc_init(ipu, dev, ipu_base + devtype->cm_ofs +
948 			IPU_CM_DC_REG_OFS, ipu_base + devtype->dc_tmpl_ofs);
955 			devtype->cm_ofs + IPU_CM_DMFC_REG_OFS, ipu_clk);
961 	ret = ipu_dp_init(ipu, dev, ipu_base + devtype->srm_ofs);
968 			devtype->cm_ofs + IPU_CM_SMFC_REG_OFS);
1313 	const struct ipu_devtype *devtype;
1315 	devtype = of_device_get_match_data(&pdev->dev);
1316 	if (!devtype)
1347 	ipu->devtype = devtype;
1348 	ipu->ipu_type = devtype->type;
1355 			ipu_base + devtype->cm_ofs);
1357 			ipu_base + devtype->cm_ofs + IPU_CM_IDMAC_REG_OFS);
1359 			ipu_base + devtype->cpmem_ofs);
1361 			ipu_base + devtype->csi0_ofs);
1363 			ipu_base + devtype->csi1_ofs);
1365 			ipu_base + devtype->ic_ofs);
1367 			ipu_base + devtype->disp0_ofs);
1369 			ipu_base + devtype->disp1_ofs);
1371 			ipu_base + devtype->srm_ofs);
1373 			ipu_base + devtype->tpm_ofs);
1375 			ipu_base + devtype->cm_ofs + IPU_CM_DC_REG_OFS);
1377 			ipu_base + devtype->cm_ofs + IPU_CM_IC_REG_OFS);
1379 			ipu_base + devtype->cm_ofs + IPU_CM_DMFC_REG_OFS);
1381 			ipu_base + devtype->vdi_ofs);
1384 			ipu_base + devtype->cm_ofs, PAGE_SIZE);
1386 			ipu_base + devtype->cm_ofs + IPU_CM_IDMAC_REG_OFS,
1439 	dev_info(&pdev->dev, "%s probed\n", devtype->name);