Lines Matching refs:disp

108  * @disp: Back pointer to struct zynqmp_disp
117 struct zynqmp_disp *disp;
357 static u32 zynqmp_disp_avbuf_read(struct zynqmp_disp *disp, int reg)
359 return readl(disp->avbuf.base + reg);
362 static void zynqmp_disp_avbuf_write(struct zynqmp_disp *disp, int reg, u32 val)
364 writel(val, disp->avbuf.base + reg);
374 * @disp: Display controller
380 static void zynqmp_disp_avbuf_set_format(struct zynqmp_disp *disp,
387 val = zynqmp_disp_avbuf_read(disp, ZYNQMP_DISP_AV_BUF_FMT);
392 zynqmp_disp_avbuf_write(disp, ZYNQMP_DISP_AV_BUF_FMT, val);
399 zynqmp_disp_avbuf_write(disp, reg, fmt->sf[i]);
405 * @disp: Display controller
415 zynqmp_disp_avbuf_set_clocks_sources(struct zynqmp_disp *disp,
428 zynqmp_disp_avbuf_write(disp, ZYNQMP_DISP_AV_BUF_CLK_SRC, val);
433 * @disp: Display controller
437 static void zynqmp_disp_avbuf_enable_channels(struct zynqmp_disp *disp)
447 zynqmp_disp_avbuf_write(disp, ZYNQMP_DISP_AV_BUF_CHBUF(i),
455 zynqmp_disp_avbuf_write(disp, ZYNQMP_DISP_AV_BUF_CHBUF(i),
461 * @disp: Display controller
465 static void zynqmp_disp_avbuf_disable_channels(struct zynqmp_disp *disp)
470 zynqmp_disp_avbuf_write(disp, ZYNQMP_DISP_AV_BUF_CHBUF(i),
476 * @disp: Display controller
480 static void zynqmp_disp_avbuf_enable_audio(struct zynqmp_disp *disp)
484 val = zynqmp_disp_avbuf_read(disp, ZYNQMP_DISP_AV_BUF_OUTPUT);
488 zynqmp_disp_avbuf_write(disp, ZYNQMP_DISP_AV_BUF_OUTPUT, val);
493 * @disp: Display controller
497 static void zynqmp_disp_avbuf_disable_audio(struct zynqmp_disp *disp)
501 val = zynqmp_disp_avbuf_read(disp, ZYNQMP_DISP_AV_BUF_OUTPUT);
505 zynqmp_disp_avbuf_write(disp, ZYNQMP_DISP_AV_BUF_OUTPUT, val);
510 * @disp: Display controller
515 static void zynqmp_disp_avbuf_enable_video(struct zynqmp_disp *disp,
520 val = zynqmp_disp_avbuf_read(disp, ZYNQMP_DISP_AV_BUF_OUTPUT);
535 zynqmp_disp_avbuf_write(disp, ZYNQMP_DISP_AV_BUF_OUTPUT, val);
540 * @disp: Display controller
545 static void zynqmp_disp_avbuf_disable_video(struct zynqmp_disp *disp,
550 val = zynqmp_disp_avbuf_read(disp, ZYNQMP_DISP_AV_BUF_OUTPUT);
558 zynqmp_disp_avbuf_write(disp, ZYNQMP_DISP_AV_BUF_OUTPUT, val);
563 * @disp: Display controller
567 static void zynqmp_disp_avbuf_enable(struct zynqmp_disp *disp)
569 zynqmp_disp_avbuf_write(disp, ZYNQMP_DISP_AV_BUF_SRST_REG, 0);
574 * @disp: Display controller
578 static void zynqmp_disp_avbuf_disable(struct zynqmp_disp *disp)
580 zynqmp_disp_avbuf_write(disp, ZYNQMP_DISP_AV_BUF_SRST_REG,
588 static void zynqmp_disp_blend_write(struct zynqmp_disp *disp, int reg, u32 val)
590 writel(val, disp->blend.base + reg);
636 * @disp: Display controller
641 static void zynqmp_disp_blend_set_output_format(struct zynqmp_disp *disp,
657 zynqmp_disp_blend_write(disp, ZYNQMP_DISP_V_BLEND_OUTPUT_VID_FMT, fmt);
667 zynqmp_disp_blend_write(disp,
672 zynqmp_disp_blend_write(disp,
679 * @disp: Display controller
688 static void zynqmp_disp_blend_set_bg_color(struct zynqmp_disp *disp,
691 zynqmp_disp_blend_write(disp, ZYNQMP_DISP_V_BLEND_BG_CLR_0, rcr);
692 zynqmp_disp_blend_write(disp, ZYNQMP_DISP_V_BLEND_BG_CLR_1, gy);
693 zynqmp_disp_blend_write(disp, ZYNQMP_DISP_V_BLEND_BG_CLR_2, bcb);
698 * @disp: Display controller
702 void zynqmp_disp_blend_set_global_alpha(struct zynqmp_disp *disp,
705 zynqmp_disp_blend_write(disp, ZYNQMP_DISP_V_BLEND_SET_GLOBAL_ALPHA,
712 * @disp: Display controller
721 static void zynqmp_disp_blend_layer_set_csc(struct zynqmp_disp *disp,
748 zynqmp_disp_blend_write(disp, reg + 0, coeffs[i + swap[0]]);
749 zynqmp_disp_blend_write(disp, reg + 4, coeffs[i + swap[1]]);
750 zynqmp_disp_blend_write(disp, reg + 8, coeffs[i + swap[2]]);
759 zynqmp_disp_blend_write(disp, reg + i * 4, offsets[i]);
764 * @disp: Display controller
767 static void zynqmp_disp_blend_layer_enable(struct zynqmp_disp *disp,
779 zynqmp_disp_blend_write(disp,
791 zynqmp_disp_blend_layer_set_csc(disp, layer, coeffs, offsets);
796 * @disp: Display controller
799 static void zynqmp_disp_blend_layer_disable(struct zynqmp_disp *disp,
802 zynqmp_disp_blend_write(disp,
806 zynqmp_disp_blend_layer_set_csc(disp, layer, csc_zero_matrix,
814 static void zynqmp_disp_audio_write(struct zynqmp_disp *disp, int reg, u32 val)
816 writel(val, disp->audio.base + reg);
821 * @disp: Display controller
826 static void zynqmp_disp_audio_enable(struct zynqmp_disp *disp)
829 zynqmp_disp_audio_write(disp, ZYNQMP_DISP_AUD_SOFT_RESET, 0);
830 zynqmp_disp_audio_write(disp, ZYNQMP_DISP_AUD_MIXER_VOLUME,
836 * @disp: Display controller
840 static void zynqmp_disp_audio_disable(struct zynqmp_disp *disp)
842 zynqmp_disp_audio_write(disp, ZYNQMP_DISP_AUD_SOFT_RESET,
914 zynqmp_disp_avbuf_enable_video(layer->disp, layer);
915 zynqmp_disp_blend_layer_enable(layer->disp, layer);
929 if (layer->disp->dpsub->dma_enabled) {
934 zynqmp_disp_avbuf_disable_video(layer->disp, layer);
935 zynqmp_disp_blend_layer_disable(layer->disp, layer);
953 zynqmp_disp_avbuf_set_format(layer->disp, layer, layer->disp_fmt);
955 if (!layer->disp->dpsub->dma_enabled)
993 if (!layer->disp->dpsub->dma_enabled)
1019 dev_err(layer->disp->dev,
1033 * @disp: Display controller
1038 static void zynqmp_disp_layer_release_dma(struct zynqmp_disp *disp,
1043 if (!layer->info || !disp->dpsub->dma_enabled)
1060 * @disp: Display controller
1062 static void zynqmp_disp_destroy_layers(struct zynqmp_disp *disp)
1066 for (i = 0; i < ARRAY_SIZE(disp->layers); i++)
1067 zynqmp_disp_layer_release_dma(disp, &disp->layers[i]);
1072 * @disp: Display controller
1079 static int zynqmp_disp_layer_request_dma(struct zynqmp_disp *disp,
1086 if (!disp->dpsub->dma_enabled)
1095 dma->chan = dma_request_chan(disp->dev, dma_channel_name);
1097 ret = dev_err_probe(disp->dev, PTR_ERR(dma->chan),
1109 * @disp: Display controller
1113 static int zynqmp_disp_create_layers(struct zynqmp_disp *disp)
1131 for (i = 0; i < ARRAY_SIZE(disp->layers); i++) {
1132 struct zynqmp_disp_layer *layer = &disp->layers[i];
1135 layer->disp = disp;
1138 ret = zynqmp_disp_layer_request_dma(disp, layer);
1142 disp->dpsub->layers[i] = layer;
1148 zynqmp_disp_destroy_layers(disp);
1158 * @disp: Display controller
1160 void zynqmp_disp_enable(struct zynqmp_disp *disp)
1162 zynqmp_disp_blend_set_output_format(disp, ZYNQMP_DPSUB_FORMAT_RGB);
1163 zynqmp_disp_blend_set_bg_color(disp, 0, 0, 0);
1165 zynqmp_disp_avbuf_enable(disp);
1167 zynqmp_disp_avbuf_set_clocks_sources(disp, disp->dpsub->vid_clk_from_ps,
1168 disp->dpsub->aud_clk_from_ps,
1169 disp->dpsub->vid_clk_from_ps);
1170 zynqmp_disp_avbuf_enable_channels(disp);
1171 zynqmp_disp_avbuf_enable_audio(disp);
1173 zynqmp_disp_audio_enable(disp);
1178 * @disp: Display controller
1180 void zynqmp_disp_disable(struct zynqmp_disp *disp)
1182 zynqmp_disp_audio_disable(disp);
1184 zynqmp_disp_avbuf_disable_audio(disp);
1185 zynqmp_disp_avbuf_disable_channels(disp);
1186 zynqmp_disp_avbuf_disable(disp);
1191 * @disp: Display controller
1196 int zynqmp_disp_setup_clock(struct zynqmp_disp *disp,
1203 ret = clk_set_rate(disp->dpsub->vid_clk, mode_clock);
1205 dev_err(disp->dev, "failed to set the video clock\n");
1209 rate = clk_get_rate(disp->dpsub->vid_clk);
1212 dev_info(disp->dev,
1216 dev_dbg(disp->dev,
1230 struct zynqmp_disp *disp;
1233 disp = kzalloc(sizeof(*disp), GFP_KERNEL);
1234 if (!disp)
1237 disp->dev = &pdev->dev;
1238 disp->dpsub = dpsub;
1240 disp->blend.base = devm_platform_ioremap_resource_byname(pdev, "blend");
1241 if (IS_ERR(disp->blend.base)) {
1242 ret = PTR_ERR(disp->blend.base);
1246 disp->avbuf.base = devm_platform_ioremap_resource_byname(pdev, "av_buf");
1247 if (IS_ERR(disp->avbuf.base)) {
1248 ret = PTR_ERR(disp->avbuf.base);
1252 disp->audio.base = devm_platform_ioremap_resource_byname(pdev, "aud");
1253 if (IS_ERR(disp->audio.base)) {
1254 ret = PTR_ERR(disp->audio.base);
1258 ret = zynqmp_disp_create_layers(disp);
1262 if (disp->dpsub->dma_enabled) {
1265 layer = &disp->layers[ZYNQMP_DPSUB_LAYER_VID];
1269 dpsub->disp = disp;
1274 kfree(disp);
1280 struct zynqmp_disp *disp = dpsub->disp;
1282 zynqmp_disp_destroy_layers(disp);