drm/xe/xe_pat.c

147 u16 xe_pat_index_get_coh_mode(struct xe_device *xe, u16 pat_index)
149 	WARN_ON(pat_index >= xe->pat.n_entries);
150 	return xe->pat.table[pat_index].coh_mode;
175 	struct xe_device *xe = gt_to_xe(gt);
184 	for (i = 0; i < xe->pat.n_entries; i++) {
194 	xe_assert(xe, !err);
204 	struct xe_device *xe = gt_to_xe(gt);
213 	for (i = 0; i < xe->pat.n_entries; i++) {
225 	xe_assert(xe, !err);
235 	struct xe_device *xe = gt_to_xe(gt);
244 	for (i = 0; i < xe->pat.n_entries; i++) {
254 	xe_assert(xe, !err);
264 	struct xe_device *xe = gt_to_xe(gt);
273 	for (i = 0; i < xe->pat.n_entries; i++) {
288 	xe_assert(xe, !err);
323 	struct xe_device *xe = gt_to_xe(gt);
333 	for (i = 0; i < xe->pat.n_entries; i++) {
370 	xe_assert(xe, !err);
379 void xe_pat_init_early(struct xe_device *xe)
381 	if (GRAPHICS_VER(xe) == 20) {
382 		xe->pat.ops = &xe2_pat_ops;
383 		xe->pat.table = xe2_pat_table;
384 		xe->pat.n_entries = ARRAY_SIZE(xe2_pat_table);
385 		xe->pat.idx[XE_CACHE_NONE] = 3;
386 		xe->pat.idx[XE_CACHE_WT] = 15;
387 		xe->pat.idx[XE_CACHE_WB] = 2;
388 		xe->pat.idx[XE_CACHE_NONE_COMPRESSION] = 12; /*Applicable on xe2 and beyond */
389 	} else if (xe->info.platform == XE_METEORLAKE) {
390 		xe->pat.ops = &xelpg_pat_ops;
391 		xe->pat.table = xelpg_pat_table;
392 		xe->pat.n_entries = ARRAY_SIZE(xelpg_pat_table);
393 		xe->pat.idx[XE_CACHE_NONE] = 2;
394 		xe->pat.idx[XE_CACHE_WT] = 1;
395 		xe->pat.idx[XE_CACHE_WB] = 3;
396 	} else if (xe->info.platform == XE_PVC) {
397 		xe->pat.ops = &xehpc_pat_ops;
398 		xe->pat.table = xehpc_pat_table;
399 		xe->pat.n_entries = ARRAY_SIZE(xehpc_pat_table);
400 		xe->pat.idx[XE_CACHE_NONE] = 0;
401 		xe->pat.idx[XE_CACHE_WT] = 2;
402 		xe->pat.idx[XE_CACHE_WB] = 3;
403 	} else if (xe->info.platform == XE_DG2) {
408 		xe->pat.ops = &xehp_pat_ops;
409 		xe->pat.table = xelp_pat_table;
410 		xe->pat.n_entries = ARRAY_SIZE(xelp_pat_table);
411 		xe->pat.idx[XE_CACHE_NONE] = 3;
412 		xe->pat.idx[XE_CACHE_WT] = 2;
413 		xe->pat.idx[XE_CACHE_WB] = 0;
414 	} else if (GRAPHICS_VERx100(xe) <= 1210) {
415 		WARN_ON_ONCE(!IS_DGFX(xe) && !xe->info.has_llc);
416 		xe->pat.ops = &xelp_pat_ops;
417 		xe->pat.table = xelp_pat_table;
418 		xe->pat.n_entries = ARRAY_SIZE(xelp_pat_table);
419 		xe->pat.idx[XE_CACHE_NONE] = 3;
420 		xe->pat.idx[XE_CACHE_WT] = 2;
421 		xe->pat.idx[XE_CACHE_WB] = 0;
431 		drm_err(&xe->drm, "Missing PAT table for platform with graphics version %d.%02d!\n",
432 			GRAPHICS_VER(xe), GRAPHICS_VERx100(xe) % 100);
436 	if (IS_SRIOV_VF(xe))
437 		xe->pat.ops = NULL;
439 	xe_assert(xe, !xe->pat.ops || xe->pat.ops->dump);
440 	xe_assert(xe, !xe->pat.ops || xe->pat.ops->program_graphics);
441 	xe_assert(xe, !xe->pat.ops || MEDIA_VER(xe) < 13 || xe->pat.ops->program_media);
446 	struct xe_device *xe = gt_to_xe(gt);
448 	if (!xe->pat.ops)
452 		xe->pat.ops->program_media(gt, xe->pat.table, xe->pat.n_entries);
454 		xe->pat.ops->program_graphics(gt, xe->pat.table, xe->pat.n_entries);
459 	struct xe_device *xe = gt_to_xe(gt);
461 	if (!xe->pat.ops)
464 	xe->pat.ops->dump(gt, p);