drm/xe/xe_mmio.c

32 _resize_bar(struct xe_device *xe, int resno, resource_size_t size)
34 	struct pci_dev *pdev = to_pci_dev(xe->drm.dev);
43 		drm_info(&xe->drm, "Failed to resize BAR%d to %dM (%pe). Consider enabling 'Resizable BAR' support in your BIOS\n",
48 	drm_info(&xe->drm, "BAR%d resized to %dM\n", resno, 1 << bar_size);
55 static void xe_resize_vram_bar(struct xe_device *xe)
58 	struct pci_dev *pdev = to_pci_dev(xe->drm.dev);
83 			drm_info(&xe->drm,
101 	drm_info(&xe->drm, "Attempting to resize bar from %lluMiB -> %lluMiB\n",
114 		drm_info(&xe->drm, "Can't resize VRAM BAR - platform support is missing. Consider enabling 'Resizable BAR' support in your BIOS\n");
121 	_resize_bar(xe, LMEM_BAR, rebar_size);
141 static int xe_determine_lmem_bar_size(struct xe_device *xe)
143 	struct pci_dev *pdev = to_pci_dev(xe->drm.dev);
146 		drm_err(&xe->drm, "pci resource is not valid\n");
150 	xe_resize_vram_bar(xe);
152 	xe->mem.vram.io_start = pci_resource_start(pdev, LMEM_BAR);
153 	xe->mem.vram.io_size = pci_resource_len(pdev, LMEM_BAR);
154 	if (!xe->mem.vram.io_size)
157 	/* XXX: Need to change when xe link code is ready */
158 	xe->mem.vram.dpa_base = 0;
161 	xe->mem.vram.mapping = ioremap_wc(xe->mem.vram.io_start, xe->mem.vram.io_size);
168 	struct xe_device *xe = gt_to_xe(gt);
172 	if (GRAPHICS_VER(xe) >= 20) {
192 		xe_assert_msg(xe, offset == (xe_mmio_read64_2x32(gt, GSMBASE) - ccs_size),
224 	struct xe_device *xe = tile_to_xe(tile);
235 	if (unlikely(xe->info.platform == XE_DG1)) {
236 		*tile_size = pci_resource_len(to_pci_dev(xe->drm.dev), LMEM_BAR);
245 	if (xe->info.has_flat_ccs) {
257 int xe_mmio_probe_vram(struct xe_device *xe)
269 	if (!IS_DGFX(xe))
273 	tile = xe_device_get_root_tile(xe);
278 	err = xe_determine_lmem_bar_size(xe);
282 	drm_info(&xe->drm, "VISIBLE VRAM: %pa, %pa\n", &xe->mem.vram.io_start,
283 		 &xe->mem.vram.io_size);
285 	io_size = xe->mem.vram.io_size;
288 	for_each_tile(tile, xe, id) {
294 		tile->mem.vram.io_start = xe->mem.vram.io_start + tile_offset;
298 			drm_err(&xe->drm, "Tile without any CPU visible VRAM. Aborting.\n");
302 		tile->mem.vram.dpa_base = xe->mem.vram.dpa_base + tile_offset;
304 		tile->mem.vram.mapping = xe->mem.vram.mapping + tile_offset;
307 			drm_info(&xe->drm, "Small BAR device\n");
308 		drm_info(&xe->drm, "VRAM[%u, %u]: Actual physical size %pa, usable size exclude stolen %pa, CPU accessible size %pa\n", id,
310 		drm_info(&xe->drm, "VRAM[%u, %u]: DPA range: [%pa-%llx], io range: [%pa-%llx]\n", id, tile->id,
318 		if (total_size > xe->mem.vram.io_size) {
319 			drm_info(&xe->drm, "VRAM: %pa is larger than resource %pa\n",
320 				 &total_size, &xe->mem.vram.io_size);
326 	xe->mem.vram.actual_physical_size = total_size;
328 	drm_info(&xe->drm, "Total VRAM: %pa, %pa\n", &xe->mem.vram.io_start,
329 		 &xe->mem.vram.actual_physical_size);
330 	drm_info(&xe->drm, "Available VRAM: %pa, %pa\n", &xe->mem.vram.io_start,
336 void xe_mmio_probe_tiles(struct xe_device *xe)
338 	size_t tile_mmio_size = SZ_16M, tile_mmio_ext_size = xe->info.tile_mmio_ext_size;
339 	u8 id, tile_count = xe->info.tile_count;
340 	struct xe_gt *gt = xe_root_mmio_gt(xe);
348 	if (!xe->info.skip_mtcfg) {
351 		if (tile_count < xe->info.tile_count) {
352 			drm_info(&xe->drm, "tile_count: %d, reduced_tile_count %d\n",
353 					xe->info.tile_count, tile_count);
354 			xe->info.tile_count = tile_count;
360 			xe->info.gt_count = xe->info.tile_count;
364 	regs = xe->mmio.regs;
365 	for_each_tile(tile, xe, id) {
377 	if (xe->info.has_mmio_ext) {
378 		regs = xe->mmio.regs + tile_mmio_size * tile_count;
380 		for_each_tile(tile, xe, id) {
391 	struct xe_device *xe = arg;
393 	pci_iounmap(to_pci_dev(xe->drm.dev), xe->mmio.regs);
394 	if (xe->mem.vram.mapping)
395 		iounmap(xe->mem.vram.mapping);
398 int xe_mmio_init(struct xe_device *xe)
400 	struct xe_tile *root_tile = xe_device_get_root_tile(xe);
401 	struct pci_dev *pdev = to_pci_dev(xe->drm.dev);
409 	xe->mmio.size = pci_resource_len(pdev, mmio_bar);
410 	xe->mmio.regs = pci_iomap(pdev, mmio_bar, 0);
411 	if (xe->mmio.regs == NULL) {
412 		drm_err(&xe->drm, "failed to map registers\n");
418 	root_tile->mmio.regs = xe->mmio.regs;
420 	return drmm_add_action_or_reset(&xe->drm, mmio_fini, xe);