Lines Matching refs:pc
70 pc_to_guc(struct xe_guc_pc *pc)
72 return container_of(pc, struct xe_guc, pc);
76 pc_to_xe(struct xe_guc_pc *pc)
78 struct xe_guc *guc = pc_to_guc(pc);
85 pc_to_gt(struct xe_guc_pc *pc)
87 return container_of(pc, struct xe_gt, uc.guc.pc);
91 pc_to_maps(struct xe_guc_pc *pc)
93 return &pc->bo->vmap;
108 static int wait_for_pc_state(struct xe_guc_pc *pc,
114 xe_device_assert_mem_access(pc_to_xe(pc));
117 if (slpc_shared_data_read(pc, header.global_state) == state)
130 static int pc_action_reset(struct xe_guc_pc *pc)
132 struct xe_guc_ct *ct = &pc_to_guc(pc)->ct;
137 xe_bo_ggtt_addr(pc->bo),
143 drm_err(&pc_to_xe(pc)->drm, "GuC PC reset: %pe", ERR_PTR(ret));
148 static int pc_action_shutdown(struct xe_guc_pc *pc)
150 struct xe_guc_ct *ct = &pc_to_guc(pc)->ct;
155 xe_bo_ggtt_addr(pc->bo),
161 drm_err(&pc_to_xe(pc)->drm, "GuC PC shutdown %pe",
167 static int pc_action_query_task_state(struct xe_guc_pc *pc)
169 struct xe_guc_ct *ct = &pc_to_guc(pc)->ct;
174 xe_bo_ggtt_addr(pc->bo),
178 if (wait_for_pc_state(pc, SLPC_GLOBAL_STATE_RUNNING))
184 drm_err(&pc_to_xe(pc)->drm,
190 static int pc_action_set_param(struct xe_guc_pc *pc, u8 id, u32 value)
192 struct xe_guc_ct *ct = &pc_to_guc(pc)->ct;
201 if (wait_for_pc_state(pc, SLPC_GLOBAL_STATE_RUNNING))
206 drm_err(&pc_to_xe(pc)->drm, "GuC PC set param failed: %pe",
212 static int pc_action_setup_gucrc(struct xe_guc_pc *pc, u32 mode)
214 struct xe_guc_ct *ct = &pc_to_guc(pc)->ct;
223 drm_err(&pc_to_xe(pc)->drm, "GuC RC enable failed: %pe",
240 static u32 pc_get_min_freq(struct xe_guc_pc *pc)
245 slpc_shared_data_read(pc, task_state_data.freq));
250 static void pc_set_manual_rp_ctrl(struct xe_guc_pc *pc, bool enable)
252 struct xe_gt *gt = pc_to_gt(pc);
259 static void pc_set_cur_freq(struct xe_guc_pc *pc, u32 freq)
261 struct xe_gt *gt = pc_to_gt(pc);
264 pc_set_manual_rp_ctrl(pc, true);
273 pc_set_manual_rp_ctrl(pc, false);
276 static int pc_set_min_freq(struct xe_guc_pc *pc, u32 freq)
282 if (freq < pc->rpn_freq || freq > pc->rp0_freq)
289 pc_action_set_param(pc, SLPC_PARAM_IGNORE_EFFICIENT_FREQUENCY,
290 freq < pc->rpe_freq);
292 return pc_action_set_param(pc,
297 static int pc_get_max_freq(struct xe_guc_pc *pc)
302 slpc_shared_data_read(pc, task_state_data.freq));
307 static int pc_set_max_freq(struct xe_guc_pc *pc, u32 freq)
314 if (freq < pc->rpn_freq || freq > pc->rp0_freq)
317 return pc_action_set_param(pc,
322 static void mtl_update_rpe_value(struct xe_guc_pc *pc)
324 struct xe_gt *gt = pc_to_gt(pc);
332 pc->rpe_freq = decode_freq(REG_FIELD_GET(MTL_RPE_MASK, reg));
335 static void tgl_update_rpe_value(struct xe_guc_pc *pc)
337 struct xe_gt *gt = pc_to_gt(pc);
351 pc->rpe_freq = REG_FIELD_GET(RPE_MASK, reg) * GT_FREQUENCY_MULTIPLIER;
354 static void pc_update_rp_values(struct xe_guc_pc *pc)
356 struct xe_gt *gt = pc_to_gt(pc);
360 mtl_update_rpe_value(pc);
362 tgl_update_rpe_value(pc);
369 pc->rpn_freq = min(pc->rpn_freq, pc->rpe_freq);
374 * @pc: The GuC PC
378 u32 xe_guc_pc_get_act_freq(struct xe_guc_pc *pc)
380 struct xe_gt *gt = pc_to_gt(pc);
404 * @pc: The GuC PC
410 int xe_guc_pc_get_cur_freq(struct xe_guc_pc *pc, u32 *freq)
412 struct xe_gt *gt = pc_to_gt(pc);
437 * @pc: The GuC PC
441 u32 xe_guc_pc_get_rp0_freq(struct xe_guc_pc *pc)
443 return pc->rp0_freq;
448 * @pc: The GuC PC
452 u32 xe_guc_pc_get_rpe_freq(struct xe_guc_pc *pc)
454 struct xe_gt *gt = pc_to_gt(pc);
458 pc_update_rp_values(pc);
461 return pc->rpe_freq;
466 * @pc: The GuC PC
470 u32 xe_guc_pc_get_rpn_freq(struct xe_guc_pc *pc)
472 return pc->rpn_freq;
477 * @pc: The GuC PC
483 int xe_guc_pc_get_min_freq(struct xe_guc_pc *pc, u32 *freq)
485 struct xe_gt *gt = pc_to_gt(pc);
488 xe_device_mem_access_get(pc_to_xe(pc));
489 mutex_lock(&pc->freq_lock);
490 if (!pc->freq_ready) {
504 ret = pc_action_query_task_state(pc);
508 *freq = pc_get_min_freq(pc);
513 mutex_unlock(&pc->freq_lock);
514 xe_device_mem_access_put(pc_to_xe(pc));
520 * @pc: The GuC PC
527 int xe_guc_pc_set_min_freq(struct xe_guc_pc *pc, u32 freq)
531 xe_device_mem_access_get(pc_to_xe(pc));
532 mutex_lock(&pc->freq_lock);
533 if (!pc->freq_ready) {
539 ret = pc_set_min_freq(pc, freq);
543 pc->user_requested_min = freq;
546 mutex_unlock(&pc->freq_lock);
547 xe_device_mem_access_put(pc_to_xe(pc));
554 * @pc: The GuC PC
560 int xe_guc_pc_get_max_freq(struct xe_guc_pc *pc, u32 *freq)
564 xe_device_mem_access_get(pc_to_xe(pc));
565 mutex_lock(&pc->freq_lock);
566 if (!pc->freq_ready) {
572 ret = pc_action_query_task_state(pc);
576 *freq = pc_get_max_freq(pc);
579 mutex_unlock(&pc->freq_lock);
580 xe_device_mem_access_put(pc_to_xe(pc));
586 * @pc: The GuC PC
593 int xe_guc_pc_set_max_freq(struct xe_guc_pc *pc, u32 freq)
597 xe_device_mem_access_get(pc_to_xe(pc));
598 mutex_lock(&pc->freq_lock);
599 if (!pc->freq_ready) {
605 ret = pc_set_max_freq(pc, freq);
609 pc->user_requested_max = freq;
612 mutex_unlock(&pc->freq_lock);
613 xe_device_mem_access_put(pc_to_xe(pc));
619 * @pc: XE_GuC_PC instance
621 enum xe_gt_idle_state xe_guc_pc_c_status(struct xe_guc_pc *pc)
623 struct xe_gt *gt = pc_to_gt(pc);
650 * @pc: Xe_GuC_PC instance
652 u64 xe_guc_pc_rc6_residency(struct xe_guc_pc *pc)
654 struct xe_gt *gt = pc_to_gt(pc);
666 * @pc: Xe_GuC_PC instance
668 u64 xe_guc_pc_mc6_residency(struct xe_guc_pc *pc)
670 struct xe_gt *gt = pc_to_gt(pc);
680 static void mtl_init_fused_rp_values(struct xe_guc_pc *pc)
682 struct xe_gt *gt = pc_to_gt(pc);
685 xe_device_assert_mem_access(pc_to_xe(pc));
692 pc->rp0_freq = decode_freq(REG_FIELD_GET(MTL_RP0_CAP_MASK, reg));
694 pc->rpn_freq = decode_freq(REG_FIELD_GET(MTL_RPN_CAP_MASK, reg));
697 static void tgl_init_fused_rp_values(struct xe_guc_pc *pc)
699 struct xe_gt *gt = pc_to_gt(pc);
703 xe_device_assert_mem_access(pc_to_xe(pc));
709 pc->rp0_freq = REG_FIELD_GET(RP0_MASK, reg) * GT_FREQUENCY_MULTIPLIER;
710 pc->rpn_freq = REG_FIELD_GET(RPN_MASK, reg) * GT_FREQUENCY_MULTIPLIER;
713 static void pc_init_fused_rp_values(struct xe_guc_pc *pc)
715 struct xe_gt *gt = pc_to_gt(pc);
719 mtl_init_fused_rp_values(pc);
721 tgl_init_fused_rp_values(pc);
727 * @pc: Xe_GuC_PC instance
729 void xe_guc_pc_init_early(struct xe_guc_pc *pc)
731 struct xe_gt *gt = pc_to_gt(pc);
734 pc_init_fused_rp_values(pc);
735 pc_set_cur_freq(pc, pc->rp0_freq);
738 static int pc_adjust_freq_bounds(struct xe_guc_pc *pc)
742 lockdep_assert_held(&pc->freq_lock);
744 ret = pc_action_query_task_state(pc);
753 if (pc_get_max_freq(pc) > pc->rp0_freq)
754 pc_set_max_freq(pc, pc->rp0_freq);
760 if (pc_get_min_freq(pc) > pc->rp0_freq)
761 pc_set_min_freq(pc, pc->rp0_freq);
766 static int pc_adjust_requested_freq(struct xe_guc_pc *pc)
770 lockdep_assert_held(&pc->freq_lock);
772 if (pc->user_requested_min != 0) {
773 ret = pc_set_min_freq(pc, pc->user_requested_min);
778 if (pc->user_requested_max != 0) {
779 ret = pc_set_max_freq(pc, pc->user_requested_max);
789 * @pc: Xe_GuC_PC instance
795 int xe_guc_pc_gucrc_disable(struct xe_guc_pc *pc)
797 struct xe_device *xe = pc_to_xe(pc);
798 struct xe_gt *gt = pc_to_gt(pc);
804 xe_device_mem_access_get(pc_to_xe(pc));
806 ret = pc_action_setup_gucrc(pc, XE_GUCRC_HOST_CONTROL);
819 xe_device_mem_access_put(pc_to_xe(pc));
823 static void pc_init_pcode_freq(struct xe_guc_pc *pc)
825 u32 min = DIV_ROUND_CLOSEST(pc->rpn_freq, GT_FREQUENCY_MULTIPLIER);
826 u32 max = DIV_ROUND_CLOSEST(pc->rp0_freq, GT_FREQUENCY_MULTIPLIER);
828 XE_WARN_ON(xe_pcode_init_min_freq_table(pc_to_gt(pc), min, max));
831 static int pc_init_freqs(struct xe_guc_pc *pc)
835 mutex_lock(&pc->freq_lock);
837 ret = pc_adjust_freq_bounds(pc);
841 ret = pc_adjust_requested_freq(pc);
845 pc_update_rp_values(pc);
847 pc_init_pcode_freq(pc);
853 pc->freq_ready = true;
856 mutex_unlock(&pc->freq_lock);
862 * @pc: Xe_GuC_PC instance
864 int xe_guc_pc_start(struct xe_guc_pc *pc)
866 struct xe_device *xe = pc_to_xe(pc);
867 struct xe_gt *gt = pc_to_gt(pc);
873 xe_device_mem_access_get(pc_to_xe(pc));
884 pc_set_cur_freq(pc, UINT_MAX);
890 memset(pc->bo->vmap.vaddr, 0, size);
891 slpc_shared_data_write(pc, header.size, size);
893 ret = pc_action_reset(pc);
897 if (wait_for_pc_state(pc, SLPC_GLOBAL_STATE_RUNNING)) {
898 drm_err(&pc_to_xe(pc)->drm, "GuC PC Start failed\n");
903 ret = pc_init_freqs(pc);
908 xe_guc_pc_gucrc_disable(pc);
913 ret = pc_action_setup_gucrc(pc, XE_GUCRC_FIRMWARE_CONTROL);
918 xe_device_mem_access_put(pc_to_xe(pc));
924 * @pc: Xe_GuC_PC instance
926 int xe_guc_pc_stop(struct xe_guc_pc *pc)
928 struct xe_device *xe = pc_to_xe(pc);
931 xe_device_mem_access_get(pc_to_xe(pc));
934 xe_gt_idle_disable_c6(pc_to_gt(pc));
939 mutex_lock(&pc->freq_lock);
940 pc->freq_ready = false;
941 mutex_unlock(&pc->freq_lock);
943 ret = pc_action_shutdown(pc);
947 if (wait_for_pc_state(pc, SLPC_GLOBAL_STATE_NOT_RUNNING)) {
948 drm_err(&pc_to_xe(pc)->drm, "GuC PC Shutdown failed\n");
953 xe_device_mem_access_put(pc_to_xe(pc));
964 struct xe_guc_pc *pc = arg;
965 struct xe_device *xe = pc_to_xe(pc);
969 xe_gt_idle_disable_c6(pc_to_gt(pc));
974 xe_force_wake_get(gt_to_fw(pc_to_gt(pc)), XE_FORCEWAKE_ALL);
975 XE_WARN_ON(xe_guc_pc_gucrc_disable(pc));
976 XE_WARN_ON(xe_guc_pc_stop(pc));
977 xe_force_wake_put(gt_to_fw(pc_to_gt(pc)), XE_FORCEWAKE_ALL);
982 * @pc: Xe_GuC_PC instance
984 int xe_guc_pc_init(struct xe_guc_pc *pc)
986 struct xe_gt *gt = pc_to_gt(pc);
996 err = drmm_mutex_init(&xe->drm, &pc->freq_lock);
1006 pc->bo = bo;
1008 err = drmm_add_action_or_reset(&xe->drm, xe_guc_pc_fini, pc);