drm/xe/xe_guc_ads.c

129 	struct xe_device *xe = ads_to_xe(ads);
131 	xe_assert(xe, ads->regset_size);
154 	struct xe_device *xe = ads_to_xe(ads);
156 	if (!xe->info.has_usm)
228 static bool needs_wa_1607983814(struct xe_device *xe)
230 	return GRAPHICS_VERx100(xe) < 1250;
268 	struct xe_device *xe = ads_to_xe(ads);
277 		real_size = xe_lrc_size(xe, class);
393 	struct xe_device *xe = ads_to_xe(ads);
402 	bo = xe_managed_bo_create_pin_map(xe, tile, guc_ads_size(ads) + MAX_GOLDEN_LRC_SIZE,
454 	struct xe_device *xe = gt_to_xe(gt);
456 	info_map_write(xe, info_map, engine_enabled_masks[GUC_RENDER_CLASS],
458 	info_map_write(xe, info_map, engine_enabled_masks[GUC_BLITTER_CLASS],
460 	info_map_write(xe, info_map, engine_enabled_masks[GUC_VIDEO_CLASS],
462 	info_map_write(xe, info_map,
465 	info_map_write(xe, info_map, engine_enabled_masks[GUC_COMPUTE_CLASS],
467 	info_map_write(xe, info_map, engine_enabled_masks[GUC_GSC_OTHER_CLASS],
473 	struct xe_device *xe = ads_to_xe(ads);
479 		if (!info_map_read(xe, &info_map,
485 			       xe_lrc_skip_size(xe));
495 	struct xe_device *xe = gt_to_xe(gt);
501 			info_map_write(xe, info_map, mapping_table[i][j],
508 	struct xe_device *xe = gt_to_xe(gt);
518 		info_map_write(xe, info_map,
558 	struct xe_device *xe = ads_to_xe(ads);
590 	if (needs_wa_1607983814(xe) && hwe->class == XE_ENGINE_CLASS_RENDER) {
667 	struct xe_device *xe = ads_to_xe(ads);
670 	if (GRAPHICS_VER(xe) >= 12 && !IS_DGFX(xe)) {
712 	struct xe_device *xe = ads_to_xe(ads);
730 	if (xe->info.has_usm) {
746 	struct xe_device *xe = ads_to_xe(ads);
762 		if (!info_map_read(xe, &info_map,
768 		real_size = xe_lrc_size(xe, class);
784 			       real_size - xe_lrc_skip_size(xe));
788 		xe_map_memcpy_to(xe, ads_to_map(ads), offset,