drm/vmwgfx/vmwgfx_kms.c

48 	struct vmw_private *dev_priv = vmw_priv(du->primary.dev);
52 	if (vmw_cmd_supported(dev_priv))
66 static void vmw_cursor_update_mob(struct vmw_private *dev_priv,
78  * @dev_priv: the private driver struct
85 static void vmw_send_define_cursor_cmd(struct vmw_private *dev_priv,
98 	cmd = VMW_CMD_RESERVE(dev_priv, cmd_size);
114 	vmw_cmd_commit_flush(dev_priv, cmd_size);
119  * @dev_priv: the private driver struct
127 static void vmw_cursor_update_image(struct vmw_private *dev_priv,
133 		vmw_cursor_update_mob(dev_priv, vps, image,
138 		vmw_send_define_cursor_cmd(dev_priv, image, width, height,
149  * @dev_priv: device to work with
157 static void vmw_cursor_update_mob(struct vmw_private *dev_priv,
180 	vmw_write(dev_priv, SVGA_REG_CURSOR_MOBID,
279 	struct vmw_private *dev_priv = vcp->base.dev->dev_private;
286 	if (!dev_priv->has_mob ||
287 	    (dev_priv->capabilities2 & SVGA_CAP2_CURSOR_MOB) == 0)
290 	mob_max_size = vmw_read(dev_priv, SVGA_REG_MOB_MAX_SIZE);
291 	cursor_max_dim = vmw_read(dev_priv, SVGA_REG_CURSOR_MAX_DIMENSION);
313 	ret = vmw_bo_create_and_populate(dev_priv, size,
325 	ret = vmw_execbuf_fence_commands(NULL, dev_priv, &fence, NULL);
343 static void vmw_cursor_update_position(struct vmw_private *dev_priv,
350 	spin_lock(&dev_priv->cursor_lock);
351 	if (dev_priv->capabilities2 & SVGA_CAP2_EXTRA_REGS) {
352 		vmw_write(dev_priv, SVGA_REG_CURSOR4_X, x);
353 		vmw_write(dev_priv, SVGA_REG_CURSOR4_Y, y);
354 		vmw_write(dev_priv, SVGA_REG_CURSOR4_SCREEN_ID, SVGA3D_INVALID_ID);
355 		vmw_write(dev_priv, SVGA_REG_CURSOR4_ON, svga_cursor_on);
356 		vmw_write(dev_priv, SVGA_REG_CURSOR4_SUBMIT, 1);
357 	} else if (vmw_is_cursor_bypass3_enabled(dev_priv)) {
358 		vmw_fifo_mem_write(dev_priv, SVGA_FIFO_CURSOR_ON, svga_cursor_on);
359 		vmw_fifo_mem_write(dev_priv, SVGA_FIFO_CURSOR_X, x);
360 		vmw_fifo_mem_write(dev_priv, SVGA_FIFO_CURSOR_Y, y);
361 		count = vmw_fifo_mem_read(dev_priv, SVGA_FIFO_CURSOR_COUNT);
362 		vmw_fifo_mem_write(dev_priv, SVGA_FIFO_CURSOR_COUNT, ++count);
364 		vmw_write(dev_priv, SVGA_REG_CURSOR_X, x);
365 		vmw_write(dev_priv, SVGA_REG_CURSOR_Y, y);
366 		vmw_write(dev_priv, SVGA_REG_CURSOR_ON, svga_cursor_on);
368 	spin_unlock(&dev_priv->cursor_lock);
465  * @dev_priv: Pointer to the device private struct.
469 void vmw_kms_legacy_hotspot_clear(struct vmw_private *dev_priv)
471 	struct drm_device *dev = &dev_priv->drm;
485 void vmw_kms_cursor_post_execbuf(struct vmw_private *dev_priv)
487 	struct drm_device *dev = &dev_priv->drm;
501 		vmw_send_define_cursor_cmd(dev_priv,
776 	struct vmw_private *dev_priv = vmw_priv(crtc->dev);
788 		vmw_cursor_update_position(dev_priv, false, 0, 0);
810 			vmw_cursor_update_image(dev_priv, vps, image,
819 	vmw_cursor_update_position(dev_priv, true,
1239  * @dev_priv: Pointer to the device private structure.
1251 int vmw_kms_readback(struct vmw_private *dev_priv,
1258 	switch (dev_priv->active_display_unit) {
1260 		return vmw_kms_sou_readback(dev_priv, file_priv, vfb,
1264 		return vmw_kms_stdu_readback(dev_priv, file_priv, vfb,
1281 static int vmw_kms_new_framebuffer_surface(struct vmw_private *dev_priv,
1289 	struct drm_device *dev = &dev_priv->drm;
1295 	if (dev_priv->active_display_unit == vmw_du_legacy)
1302 	if (!drm_any_plane_has_format(&dev_priv->drm,
1305 		drm_dbg(&dev_priv->drm,
1348 	if (!has_sm4_context(dev_priv) && format != surface->metadata.format) {
1477 	mutex_lock(&res->dev_priv->cmdbuf_mutex);
1483 	mutex_unlock(&res->dev_priv->cmdbuf_mutex);
1490 static int vmw_kms_new_framebuffer_bo(struct vmw_private *dev_priv,
1497 	struct drm_device *dev = &dev_priv->drm;
1509 	if (!drm_any_plane_has_format(&dev_priv->drm,
1512 		drm_dbg(&dev_priv->drm,
1548  * @dev_priv: Pointer to device private struct.
1555 vmw_kms_srf_ok(struct vmw_private *dev_priv, uint32_t width, uint32_t height)
1557 	if (width  > dev_priv->texture_max_width ||
1558 	    height > dev_priv->texture_max_height)
1567  * @dev_priv: Pointer to device private struct.
1577 vmw_kms_new_framebuffer(struct vmw_private *dev_priv,
1592 	if (vmw_kms_srf_ok(dev_priv, mode_cmd->width, mode_cmd->height)  &&
1595 	    dev_priv->active_display_unit == vmw_du_screen_target) {
1596 		ret = vmw_create_bo_proxy(&dev_priv->drm, mode_cmd,
1606 		ret = vmw_kms_new_framebuffer_surface(dev_priv, surface, &vfb,
1616 		ret = vmw_kms_new_framebuffer_bo(dev_priv, bo, &vfb,
1636 	struct vmw_private *dev_priv = vmw_priv(dev);
1643 	ret = vmw_user_lookup_handle(dev_priv, file_priv,
1654 	    !vmw_kms_srf_ok(dev_priv, mode_cmd->width, mode_cmd->height)) {
1656 			dev_priv->texture_max_width,
1657 			dev_priv->texture_max_height);
1662 	vfb = vmw_kms_new_framebuffer(dev_priv, bo, surface,
1663 				      !(dev_priv->capabilities & SVGA_CAP_3D),
1700 	struct vmw_private *dev_priv = vmw_priv(dev);
1710 		if (dev_priv->active_display_unit == vmw_du_screen_target &&
1711 		    (drm_rect_width(&rects[i]) > dev_priv->stdu_max_width ||
1712 		     drm_rect_height(&rects[i]) > dev_priv->stdu_max_height)) {
1736 	if (pixel_mem > dev_priv->max_primary_mem) {
1742 	if (dev_priv->active_display_unit != vmw_du_screen_target ||
1743 	    !(dev_priv->capabilities & SVGA_CAP_NO_BB_RESTRICTION)) {
1746 		if (bb_mem > dev_priv->max_primary_mem) {
1975 static int vmw_kms_generic_present(struct vmw_private *dev_priv,
1984 	return vmw_kms_sou_do_surface_dirty(dev_priv, vfb, NULL, clips,
1990 int vmw_kms_present(struct vmw_private *dev_priv,
2001 	switch (dev_priv->active_display_unit) {
2003 		ret = vmw_kms_stdu_surface_dirty(dev_priv, vfb, NULL, clips,
2008 		ret = vmw_kms_generic_present(dev_priv, file_priv, vfb, surface,
2021 	vmw_cmd_flush(dev_priv, false);
2027 vmw_kms_create_hotplug_mode_update_property(struct vmw_private *dev_priv)
2029 	if (dev_priv->hotplug_mode_update_property)
2032 	dev_priv->hotplug_mode_update_property =
2033 		drm_property_create_range(&dev_priv->drm,
2061 int vmw_kms_init(struct vmw_private *dev_priv)
2063 	struct drm_device *dev = &dev_priv->drm;
2077 	dev->mode_config.max_width = dev_priv->texture_max_width;
2078 	dev->mode_config.max_height = dev_priv->texture_max_height;
2079 	dev->mode_config.preferred_depth = dev_priv->assume_16bpp ? 16 : 32;
2083 	vmw_kms_create_hotplug_mode_update_property(dev_priv);
2085 	ret = vmw_kms_stdu_init_display(dev_priv);
2087 		ret = vmw_kms_sou_init_display(dev_priv);
2089 			ret = vmw_kms_ldu_init_display(dev_priv);
2092 	drm_info(&dev_priv->drm, "%s display unit initialized\n",
2093 		 display_unit_names[dev_priv->active_display_unit]);
2098 int vmw_kms_close(struct vmw_private *dev_priv)
2107 	drm_mode_config_cleanup(&dev_priv->drm);
2108 	if (dev_priv->active_display_unit == vmw_du_legacy)
2109 		ret = vmw_kms_ldu_close_display(dev_priv);
2174 bool vmw_kms_validate_mode_vram(struct vmw_private *dev_priv,
2179 		((dev_priv->active_display_unit == vmw_du_screen_target) ?
2180 		 dev_priv->max_primary_mem : dev_priv->vram_size);
2186  * @dev_priv: device private
2190 static int vmw_du_update_layout(struct vmw_private *dev_priv,
2193 	struct drm_device *dev = &dev_priv->drm;
2269 	struct vmw_private *dev_priv = vmw_priv(crtc->dev);
2275 		vmw_write(dev_priv, SVGA_PALETTE_BASE + i * 3 + 0, r[i] >> 8);
2276 		vmw_write(dev_priv, SVGA_PALETTE_BASE + i * 3 + 1, g[i] >> 8);
2277 		vmw_write(dev_priv, SVGA_PALETTE_BASE + i * 3 + 2, b[i] >> 8);
2293 	struct vmw_private *dev_priv = vmw_priv(dev);
2296 	num_displays = vmw_read(dev_priv, SVGA_REG_NUM_DISPLAYS);
2346 	struct vmw_private *dev_priv = vmw_priv(dev);
2360 		vmw_du_update_layout(dev_priv, 1, &def_rect);
2422 		vmw_du_update_layout(dev_priv, arg->num_outputs, drm_rects);
2433  * @dev_priv: Pointer to a device private structure.
2446 int vmw_kms_helper_dirty(struct vmw_private *dev_priv,
2460 	dirty->dev_priv = dev_priv;
2466 		list_for_each_entry(crtc, &dev_priv->drm.mode_config.crtc_list,
2486 			dirty->cmd = VMW_CMD_RESERVE(dev_priv,
2555  * @dev_priv: Pointer to the device-private struct
2562 void vmw_kms_helper_validation_finish(struct vmw_private *dev_priv,
2575 		ret = vmw_execbuf_fence_commands(file_priv, dev_priv, &fence,
2579 		vmw_execbuf_copy_fence_user(dev_priv, vmw_fpriv(file_priv),
2607 	struct vmw_private *dev_priv = res->dev_priv;
2620 	cmd = VMW_CMD_RESERVE(dev_priv, sizeof(*cmd) * num_clips);
2649 	vmw_cmd_commit(dev_priv, copy_size);
2658  * @dev_priv: Pointer to a device private struct.
2663 vmw_kms_create_implicit_placement_property(struct vmw_private *dev_priv)
2665 	if (dev_priv->implicit_placement_property)
2668 	dev_priv->implicit_placement_property =
2669 		drm_property_create_range(&dev_priv->drm,
2682 	struct vmw_private *dev_priv = vmw_priv(dev);
2684 	dev_priv->suspend_state = drm_atomic_helper_suspend(dev);
2685 	if (IS_ERR(dev_priv->suspend_state)) {
2686 		int ret = PTR_ERR(dev_priv->suspend_state);
2689 		dev_priv->suspend_state = NULL;
2709 	struct vmw_private *dev_priv = vmw_priv(dev);
2712 	if (WARN_ON(!dev_priv->suspend_state))
2715 	ret = drm_atomic_helper_resume(dev, dev_priv->suspend_state);
2716 	dev_priv->suspend_state = NULL;
2776 		if (update->dev_priv->active_display_unit == vmw_du_screen_target) {
2781 			WARN_ON(update->dev_priv->has_mob);
2802 	cmd_start = VMW_CMD_RESERVE(update->dev_priv, reserved_size);
2851 	vmw_cmd_commit(update->dev_priv, submit_size);
2853 	vmw_kms_helper_validation_finish(update->dev_priv, NULL, &val_ctx,
2877 	struct vmw_private *dev_priv = vmw_priv(dev);
2878 	u32 max_width = dev_priv->texture_max_width;
2879 	u32 max_height = dev_priv->texture_max_height;
2882 	if (dev_priv->assume_16bpp)
2885 	if (dev_priv->active_display_unit == vmw_du_screen_target) {
2886 		max_width  = min(dev_priv->stdu_max_width,  max_width);
2887 		max_height = min(dev_priv->stdu_max_height, max_height);
2896 	if (!vmw_kms_validate_mode_vram(dev_priv,
2915 	struct vmw_private *dev_priv = vmw_priv(dev);
2940 	max_width  = dev_priv->texture_max_width;
2941 	max_height = dev_priv->texture_max_height;
2943 	if (dev_priv->active_display_unit == vmw_du_screen_target) {
2944 		max_width  = min(dev_priv->stdu_max_width,  max_width);
2945 		max_height = min(dev_priv->stdu_max_height, max_height);