drm/vmwgfx/vmwgfx_ioctl.c

39 	struct vmw_private *dev_priv = vmw_priv(dev);
46 		param->value = vmw_overlay_num_overlays(dev_priv);
49 		param->value = vmw_overlay_num_free_overlays(dev_priv);
52 		param->value = vmw_supports_3d(dev_priv) ? 1 : 0;
55 		param->value = dev_priv->capabilities;
58 		param->value = dev_priv->capabilities2;
61 		param->value = vmw_fifo_caps(dev_priv);
64 		param->value = dev_priv->max_primary_mem;
68 		if ((dev_priv->capabilities & SVGA_CAP_GBOBJECTS))
72 					       dev_priv,
73 					       ((vmw_fifo_caps(dev_priv) &
80 		if ((dev_priv->capabilities & SVGA_CAP_GBOBJECTS) &&
82 			param->value = dev_priv->max_mob_pages * PAGE_SIZE / 2;
84 			param->value = dev_priv->memory_size;
87 		param->value = vmw_devcaps_size(dev_priv, vmw_fp->gb_aware);
91 		param->value = dev_priv->max_mob_pages * PAGE_SIZE;
94 		param->value = dev_priv->max_mob_size;
98 			(dev_priv->active_display_unit == vmw_du_screen_target);
101 		param->value = has_sm4_context(dev_priv);
104 		param->value = has_sm4_1_context(dev_priv);
107 		param->value = has_sm5_context(dev_priv);
110 		param->value = has_gl43_context(dev_priv);
113 		param->value = to_pci_dev(dev_priv->drm.dev)->device;
128 	struct vmw_private *dev_priv = vmw_priv(dev);
140 	size = vmw_devcaps_size(dev_priv, vmw_fp->gb_aware);
155 	ret = vmw_devcaps_copy(dev_priv, vmw_fp->gb_aware, bounce, size);
175 	struct vmw_private *dev_priv = vmw_priv(dev);
223 	ret = vmw_user_resource_lookup_handle(dev_priv, tfile, arg->sid,
230 	ret = vmw_kms_present(dev_priv, file_priv,
251 	struct vmw_private *dev_priv = vmw_priv(dev);
306 	ret = vmw_kms_readback(dev_priv, file_priv,