drm/vc4/vc4_validate_shaders.c

51 	uint32_t ip;
187 	uint64_t inst = validation_state->shader[validation_state->ip];
311 	uint64_t inst = validation_state->shader[validation_state->ip];
390 	uint64_t inst = validation_state->shader[validation_state->ip];
481 	uint64_t inst = validation_state->shader[validation_state->ip];
556 	uint64_t inst = validation_state->shader[validation_state->ip];
578 	     int ip)
592 			  validation_state->ip);
603 	uint64_t inst = validation_state->shader[validation_state->ip];
638 	int ip;
641 	for (ip = 0; ip < validation_state->max_ip; ip++) {
642 		uint64_t inst = validation_state->shader[ip];
645 		uint32_t after_delay_ip = ip + 4;
655 			validation_state->max_ip = ip + 3;
662 		if (ip - last_branch < 4) {
663 			DRM_DEBUG("Branch at %d during delay slots\n", ip);
666 		last_branch = ip;
691 			DRM_DEBUG("Branch at %d outside of shader (ip %d/%d)\n",
692 				  ip, branch_target_ip,
704 				  ip, after_delay_ip, validation_state->max_ip);
747 	uint32_t ip = validation_state->ip;
749 	if (!test_bit(ip, validation_state->branch_targets))
785 	uint32_t ip;
811 	for (ip = 0; ip < validation_state.max_ip; ip++) {
812 		uint64_t inst = validation_state.shader[ip];
815 		validation_state.ip = ip;
820 		if (ip == last_thread_switch_ip + 3) {
844 				DRM_DEBUG("Bad write at ip %d\n", ip);
854 				shader_end_ip = ip;
861 				if (ip < last_thread_switch_ip + 3) {
863 						  "last switch at ip %d\n", ip);
866 				last_thread_switch_ip = ip;
874 				DRM_DEBUG("Bad LOAD_IMM write at ip %d\n", ip);
881 					  &validation_state, ip))
884 			if (ip < last_thread_switch_ip + 3) {
885 				DRM_DEBUG("Branch in thread switch at ip %d",
886 					  ip);
893 				  "instruction %d\n", sig, ip);
900 		if (found_shader_end && ip == shader_end_ip + 2)
904 	if (ip == validation_state.max_ip) {