drm/vc4/vc4_crtc.c

57 		writel(val, vc4_crtc->regs + (offset));					\
63 		readl(vc4_crtc->regs + (offset));					\
106 	struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc);
194 			*stime = vc4_crtc->t_vblank;
196 			*etime = vc4_crtc->t_vblank;
220 static u32 vc4_get_fifo_full_level(struct vc4_crtc *vc4_crtc, u32 format)
222 	const struct vc4_crtc_data *crtc_data = vc4_crtc_to_vc4_crtc_data(vc4_crtc);
223 	const struct vc4_pv_data *pv_data = vc4_crtc_to_vc4_pv_data(vc4_crtc);
224 	struct vc4_dev *vc4 = to_vc4_dev(vc4_crtc->base.dev);
273 static u32 vc4_crtc_get_fifo_full_level_bits(struct vc4_crtc *vc4_crtc,
276 	u32 level = vc4_get_fifo_full_level(vc4_crtc, format);
308 	struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc);
328 	struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc);
329 	const struct vc4_pv_data *pv_data = vc4_crtc_to_vc4_pv_data(vc4_crtc);
354 		struct drm_printer p = drm_info_printer(&vc4_crtc->pdev->dev);
355 		dev_info(&vc4_crtc->pdev->dev, "CRTC %d regs before:\n",
357 		drm_print_regset32(&p, &vc4_crtc->regset);
437 		   vc4_crtc_get_fifo_full_level_bits(vc4_crtc, format) |
447 		struct drm_printer p = drm_info_printer(&vc4_crtc->pdev->dev);
448 		dev_info(&vc4_crtc->pdev->dev, "CRTC %d regs after:\n",
450 		drm_print_regset32(&p, &vc4_crtc->regset);
471 	struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc);
520 	struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc);
529 	if (!(of_device_is_compatible(vc4_crtc->pdev->dev.of_node,
531 	      of_device_is_compatible(vc4_crtc->pdev->dev.of_node,
541 	channel = vc4_hvs_get_fifo_from_output(vc4->hvs, vc4_crtc->data->hvs_output);
549 	pv_data = vc4_crtc_to_vc4_pv_data(vc4_crtc);
619 	struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc);
750 	struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc);
766 	struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc);
778 static void vc4_crtc_handle_page_flip(struct vc4_crtc *vc4_crtc)
780 	struct drm_crtc *crtc = &vc4_crtc->base;
784 	u32 chan = vc4_crtc->current_hvs_channel;
788 	spin_lock(&vc4_crtc->irq_lock);
789 	if (vc4_crtc->event &&
790 	    (vc4_crtc->current_dlist == HVS_READ(SCALER_DISPLACTX(chan)) ||
791 	     vc4_crtc->feeds_txp)) {
792 		drm_crtc_send_vblank_event(crtc, vc4_crtc->event);
793 		vc4_crtc->event = NULL;
804 	spin_unlock(&vc4_crtc->irq_lock);
808 void vc4_crtc_handle_vblank(struct vc4_crtc *crtc)
817 	struct vc4_crtc *vc4_crtc = data;
823 		vc4_crtc_handle_vblank(vc4_crtc);
1109 	struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc);
1110 	const struct vc4_crtc_data *crtc_data = vc4_crtc_to_vc4_crtc_data(vc4_crtc);
1113 				 &vc4_crtc->regset);
1275 	struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc);
1276 	const struct vc4_pv_data *pv_data = vc4_crtc_to_vc4_pv_data(vc4_crtc);
1302  * @vc4_crtc: CRTC Object to Initialize
1318 		    struct vc4_crtc *vc4_crtc,
1326 	struct drm_crtc *crtc = &vc4_crtc->base;
1330 	vc4_crtc->data = data;
1331 	vc4_crtc->pdev = pdev;
1332 	vc4_crtc->feeds_txp = feeds_txp;
1333 	spin_lock_init(&vc4_crtc->irq_lock);
1342 		drm_mode_crtc_set_gamma_size(crtc, ARRAY_SIZE(vc4_crtc->lut_r));
1353 		vc4_crtc->lut_r[i] = i;
1354 		vc4_crtc->lut_g[i] = i;
1355 		vc4_crtc->lut_b[i] = i;
1362 		  struct vc4_crtc *vc4_crtc,
1382 	return __vc4_crtc_init(drm, pdev, vc4_crtc, data, primary_plane,
1391 	struct vc4_crtc *vc4_crtc;
1395 	vc4_crtc = drmm_kzalloc(drm, sizeof(*vc4_crtc), GFP_KERNEL);
1396 	if (!vc4_crtc)
1398 	crtc = &vc4_crtc->base;
1404 	vc4_crtc->regs = vc4_ioremap_regs(pdev, 0);
1405 	if (IS_ERR(vc4_crtc->regs))
1406 		return PTR_ERR(vc4_crtc->regs);
1408 	vc4_crtc->regset.base = vc4_crtc->regs;
1409 	vc4_crtc->regset.regs = crtc_regs;
1410 	vc4_crtc->regset.nregs = ARRAY_SIZE(crtc_regs);
1412 	ret = vc4_crtc_init(drm, pdev, vc4_crtc, &pv_data->base,
1424 			       "vc4 crtc", vc4_crtc);
1428 	platform_set_drvdata(pdev, vc4_crtc);
1437 	struct vc4_crtc *vc4_crtc = dev_get_drvdata(dev);
1463 		.name = "vc4_crtc",