drm/v3d/v3d_sched.c

99 v3d_switch_perfmon(struct v3d_dev *v3d, struct v3d_job *job)
101 	if (job->perfmon != v3d->active_perfmon)
102 		v3d_perfmon_stop(v3d, v3d->active_perfmon, true);
104 	if (job->perfmon && v3d->active_perfmon != job->perfmon)
105 		v3d_perfmon_start(v3d, job->perfmon);
111 	struct v3d_dev *v3d = job->base.v3d;
113 	struct drm_device *dev = &v3d->drm;
123 	spin_lock_irqsave(&v3d->job_lock, irqflags);
124 	v3d->bin_job = job;
129 	spin_unlock_irqrestore(&v3d->job_lock, irqflags);
131 	v3d_invalidate_caches(v3d);
133 	fence = v3d_fence_create(v3d, V3D_BIN);
145 	v3d->queue[V3D_BIN].start_ns = file->start_ns[V3D_BIN];
147 	v3d_switch_perfmon(v3d, &job->base);
170 	struct v3d_dev *v3d = job->base.v3d;
172 	struct drm_device *dev = &v3d->drm;
178 	v3d->render_job = job;
186 	v3d_invalidate_caches(v3d);
188 	fence = v3d_fence_create(v3d, V3D_RENDER);
200 	v3d->queue[V3D_RENDER].start_ns = file->start_ns[V3D_RENDER];
202 	v3d_switch_perfmon(v3d, &job->base);
219 	struct v3d_dev *v3d = job->base.v3d;
221 	struct drm_device *dev = &v3d->drm;
224 	fence = v3d_fence_create(v3d, V3D_TFU);
228 	v3d->tfu_job = job;
236 	v3d->queue[V3D_TFU].start_ns = file->start_ns[V3D_TFU];
238 	V3D_WRITE(V3D_TFU_IIA(v3d->ver), job->args.iia);
239 	V3D_WRITE(V3D_TFU_IIS(v3d->ver), job->args.iis);
240 	V3D_WRITE(V3D_TFU_ICA(v3d->ver), job->args.ica);
241 	V3D_WRITE(V3D_TFU_IUA(v3d->ver), job->args.iua);
242 	V3D_WRITE(V3D_TFU_IOA(v3d->ver), job->args.ioa);
243 	if (v3d->ver >= 71)
245 	V3D_WRITE(V3D_TFU_IOS(v3d->ver), job->args.ios);
246 	V3D_WRITE(V3D_TFU_COEF0(v3d->ver), job->args.coef[0]);
247 	if (v3d->ver >= 71 || (job->args.coef[0] & V3D_TFU_COEF0_USECOEF)) {
248 		V3D_WRITE(V3D_TFU_COEF1(v3d->ver), job->args.coef[1]);
249 		V3D_WRITE(V3D_TFU_COEF2(v3d->ver), job->args.coef[2]);
250 		V3D_WRITE(V3D_TFU_COEF3(v3d->ver), job->args.coef[3]);
253 	V3D_WRITE(V3D_TFU_ICFG(v3d->ver), job->args.icfg | V3D_TFU_ICFG_IOC);
262 	struct v3d_dev *v3d = job->base.v3d;
264 	struct drm_device *dev = &v3d->drm;
268 	v3d->csd_job = job;
270 	v3d_invalidate_caches(v3d);
272 	fence = v3d_fence_create(v3d, V3D_CSD);
283 	v3d->queue[V3D_CSD].start_ns = file->start_ns[V3D_CSD];
285 	v3d_switch_perfmon(v3d, &job->base);
287 	csd_cfg0_reg = V3D_CSD_QUEUED_CFG0(v3d->ver);
288 	csd_cfg_reg_count = v3d->ver < 71 ? 6 : 7;
432 	struct v3d_dev *v3d = job->base.v3d;
444 			v3d_perfmon_stop(v3d, perfmon, false);
461 	struct v3d_dev *v3d = job->base.v3d;
473 		v3d_perfmon_stop(v3d, perfmon, true);
532 	struct v3d_dev *v3d = job->base.v3d;
536 	v3d->cpu_job = job;
544 	v3d->queue[V3D_CPU].start_ns = file->start_ns[V3D_CPU];
546 	trace_v3d_cpu_job_begin(&v3d->drm, job->job_type);
550 	trace_v3d_cpu_job_end(&v3d->drm, job->job_type);
555 	v3d->queue[V3D_CPU].enabled_ns += runtime;
558 	v3d->queue[V3D_CPU].jobs_sent++;
561 	v3d->queue[V3D_CPU].start_ns = 0;
570 	struct v3d_dev *v3d = job->v3d;
575 	v3d->queue[V3D_CACHE_CLEAN].start_ns = file->start_ns[V3D_CACHE_CLEAN];
577 	v3d_clean_caches(v3d);
582 	v3d->queue[V3D_CACHE_CLEAN].enabled_ns += runtime;
585 	v3d->queue[V3D_CACHE_CLEAN].jobs_sent++;
588 	v3d->queue[V3D_CACHE_CLEAN].start_ns = 0;
594 v3d_gpu_reset_for_timeout(struct v3d_dev *v3d, struct drm_sched_job *sched_job)
598 	mutex_lock(&v3d->reset_lock);
602 		drm_sched_stop(&v3d->queue[q].sched, sched_job);
608 	v3d_reset(v3d);
611 		drm_sched_resubmit_jobs(&v3d->queue[q].sched);
615 		drm_sched_start(&v3d->queue[q].sched, true);
618 	mutex_unlock(&v3d->reset_lock);
633 	struct v3d_dev *v3d = job->v3d;
643 	return v3d_gpu_reset_for_timeout(v3d, sched_job);
669 	return v3d_gpu_reset_for_timeout(job->v3d, sched_job);
676 	struct v3d_dev *v3d = job->base.v3d;
677 	u32 batches = V3D_CORE_READ(0, V3D_CSD_CURRENT_CFG4(v3d->ver));
687 	return v3d_gpu_reset_for_timeout(v3d, sched_job);
727 v3d_sched_init(struct v3d_dev *v3d)
734 	ret = drm_sched_init(&v3d->queue[V3D_BIN].sched,
739 			     NULL, "v3d_bin", v3d->drm.dev);
743 	ret = drm_sched_init(&v3d->queue[V3D_RENDER].sched,
748 			     NULL, "v3d_render", v3d->drm.dev);
752 	ret = drm_sched_init(&v3d->queue[V3D_TFU].sched,
757 			     NULL, "v3d_tfu", v3d->drm.dev);
761 	if (v3d_has_csd(v3d)) {
762 		ret = drm_sched_init(&v3d->queue[V3D_CSD].sched,
767 				     NULL, "v3d_csd", v3d->drm.dev);
771 		ret = drm_sched_init(&v3d->queue[V3D_CACHE_CLEAN].sched,
776 				     NULL, "v3d_cache_clean", v3d->drm.dev);
781 	ret = drm_sched_init(&v3d->queue[V3D_CPU].sched,
786 			     NULL, "v3d_cpu", v3d->drm.dev);
793 	v3d_sched_fini(v3d);
798 v3d_sched_fini(struct v3d_dev *v3d)
803 		if (v3d->queue[q].sched.ready)
804 			drm_sched_fini(&v3d->queue[q].sched);