Lines Matching refs:tegra_sor_writel
495 static inline void tegra_sor_writel(struct tegra_sor *sor, u32 value,
561 tegra_sor_writel(sor, value, SOR_CLK_CNTRL);
674 tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl0);
679 tegra_sor_writel(sor, value, SOR_LANE_SEQ_CTL);
706 tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl0);
711 tegra_sor_writel(sor, value, SOR_LANE_SEQ_CTL);
753 tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl0);
760 tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl0);
770 tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl0);
774 tegra_sor_writel(sor, value, sor->soc->regs->pll1);
782 tegra_sor_writel(sor, value, sor->soc->regs->pll1);
796 tegra_sor_writel(sor, value, sor->soc->regs->pll1);
801 tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl0);
856 tegra_sor_writel(sor, voltage_swing, SOR_LANE_DRIVE_CURRENT0);
857 tegra_sor_writel(sor, pre_emphasis, SOR_LANE_PREEMPHASIS0);
860 tegra_sor_writel(sor, post_cursor, SOR_LANE_POSTCURSOR0);
862 tegra_sor_writel(sor, pattern, SOR_DP_TPG);
868 tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl0);
889 tegra_sor_writel(sor, value, SOR_CLK_CNTRL);
898 tegra_sor_writel(sor, value, SOR_DP_LINKCTL0);
920 tegra_sor_writel(sor, value, sor->soc->regs->pll1);
930 tegra_sor_writel(sor, value, SOR_DP_SPARE0);
958 tegra_sor_writel(sor, 0, SOR_SUPER_STATE0);
959 tegra_sor_writel(sor, 1, SOR_SUPER_STATE0);
960 tegra_sor_writel(sor, 0, SOR_SUPER_STATE0);
965 tegra_sor_writel(sor, 0, SOR_STATE0);
966 tegra_sor_writel(sor, 1, SOR_STATE0);
967 tegra_sor_writel(sor, 0, SOR_STATE0);
977 tegra_sor_writel(sor, value, SOR_PWM_DIV);
984 tegra_sor_writel(sor, value, SOR_PWM_CTL);
1007 tegra_sor_writel(sor, value, SOR_SUPER_STATE1);
1013 tegra_sor_writel(sor, value, SOR_SUPER_STATE1);
1055 tegra_sor_writel(sor, value, SOR_PWR);
1253 tegra_sor_writel(sor, value, SOR_DP_LINKCTL0);
1272 tegra_sor_writel(sor, value, SOR_DP_CONFIG0);
1277 tegra_sor_writel(sor, value, SOR_DP_AUDIO_HBLANK_SYMBOLS);
1282 tegra_sor_writel(sor, value, SOR_DP_AUDIO_VBLANK_SYMBOLS);
1339 tegra_sor_writel(sor, value, SOR_STATE1);
1347 tegra_sor_writel(sor, value, sor->soc->regs->head_state1 + dc->pipe);
1354 tegra_sor_writel(sor, value, sor->soc->regs->head_state2 + dc->pipe);
1361 tegra_sor_writel(sor, value, sor->soc->regs->head_state3 + dc->pipe);
1368 tegra_sor_writel(sor, value, sor->soc->regs->head_state4 + dc->pipe);
1371 tegra_sor_writel(sor, 0x001, sor->soc->regs->head_state5 + dc->pipe);
1381 tegra_sor_writel(sor, value, SOR_SUPER_STATE1);
1398 tegra_sor_writel(sor, value, SOR_SUPER_STATE1);
1404 tegra_sor_writel(sor, value, SOR_SUPER_STATE1);
1431 tegra_sor_writel(sor, value, SOR_PWR);
1455 tegra_sor_writel(sor, value, sor->soc->regs->pll2);
1461 tegra_sor_writel(sor, value, sor->soc->regs->pll0);
1466 tegra_sor_writel(sor, value, sor->soc->regs->pll2);
1508 tegra_sor_writel(sor, value, SOR_STATE1);
1512 tegra_sor_writel(sor, value, SOR_CRC_CNTRL);
1516 tegra_sor_writel(sor, value, SOR_TEST);
1522 tegra_sor_writel(sor, SOR_CRCA_RESET, SOR_CRCA);
1892 tegra_sor_writel(sor, value, offset);
1904 tegra_sor_writel(sor, value, offset++);
1909 tegra_sor_writel(sor, value, offset++);
1927 tegra_sor_writel(sor, value, SOR_HDMI_AVI_INFOFRAME_CTRL);
1948 tegra_sor_writel(sor, value, SOR_HDMI_AVI_INFOFRAME_CTRL);
1958 tegra_sor_writel(sor, i << 8 | sor->output.connector.eld[i],
1968 tegra_sor_writel(sor, i << 8 | 0, SOR_AUDIO_HDA_ELD_BUFWR);
1981 tegra_sor_writel(sor, value, SOR_INT_ENABLE);
1982 tegra_sor_writel(sor, value, SOR_INT_MASK);
1987 tegra_sor_writel(sor, value, SOR_AUDIO_HDA_PRESENSE);
1992 tegra_sor_writel(sor, 0, SOR_AUDIO_HDA_PRESENSE);
1993 tegra_sor_writel(sor, 0, SOR_INT_MASK);
1994 tegra_sor_writel(sor, 0, SOR_INT_ENABLE);
2015 tegra_sor_writel(sor, value, SOR_AUDIO_CNTRL);
2018 tegra_sor_writel(sor, SOR_AUDIO_SPARE_HBR_ENABLE, SOR_AUDIO_SPARE);
2047 tegra_sor_writel(sor, value, SOR_HDMI_AUDIO_INFOFRAME_CTRL);
2058 tegra_sor_writel(sor, 0, SOR_HDMI_ACR_CTRL);
2063 tegra_sor_writel(sor, value, SOR_HDMI_SPARE);
2067 tegra_sor_writel(sor, value, SOR_HDMI_ACR_0441_SUBPACK_LOW);
2071 tegra_sor_writel(sor, value, SOR_HDMI_ACR_0441_SUBPACK_HIGH);
2075 tegra_sor_writel(sor, value, SOR_HDMI_AUDIO_N);
2078 tegra_sor_writel(sor, value, SOR_AUDIO_AVAL_0320);
2079 tegra_sor_writel(sor, 4096, SOR_AUDIO_NVAL_0320);
2081 tegra_sor_writel(sor, 20000, SOR_AUDIO_AVAL_0441);
2082 tegra_sor_writel(sor, 4704, SOR_AUDIO_NVAL_0441);
2084 tegra_sor_writel(sor, 20000, SOR_AUDIO_AVAL_0882);
2085 tegra_sor_writel(sor, 9408, SOR_AUDIO_NVAL_0882);
2087 tegra_sor_writel(sor, 20000, SOR_AUDIO_AVAL_1764);
2088 tegra_sor_writel(sor, 18816, SOR_AUDIO_NVAL_1764);
2091 tegra_sor_writel(sor, value, SOR_AUDIO_AVAL_0480);
2092 tegra_sor_writel(sor, 6144, SOR_AUDIO_NVAL_0480);
2095 tegra_sor_writel(sor, value, SOR_AUDIO_AVAL_0960);
2096 tegra_sor_writel(sor, 12288, SOR_AUDIO_NVAL_0960);
2099 tegra_sor_writel(sor, value, SOR_AUDIO_AVAL_1920);
2100 tegra_sor_writel(sor, 24576, SOR_AUDIO_NVAL_1920);
2104 tegra_sor_writel(sor, value, SOR_HDMI_AUDIO_N);
2115 tegra_sor_writel(sor, value, SOR_HDMI_AUDIO_INFOFRAME_CTRL);
2142 tegra_sor_writel(sor, value, SOR_HDMI2_CTRL);
2168 tegra_sor_writel(sor, value, SOR_HDMI2_CTRL);
2220 tegra_sor_writel(sor, 0, SOR_STATE1);
2287 tegra_sor_writel(sor, value, sor->soc->regs->pll2);
2293 tegra_sor_writel(sor, value, sor->soc->regs->pll3);
2298 tegra_sor_writel(sor, value, sor->soc->regs->pll0);
2302 tegra_sor_writel(sor, value, sor->soc->regs->pll2);
2309 tegra_sor_writel(sor, value, sor->soc->regs->pll2);
2316 tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl0);
2328 tegra_sor_writel(sor, value, SOR_LANE_SEQ_CTL);
2351 tegra_sor_writel(sor, value, SOR_CLK_CNTRL);
2359 tegra_sor_writel(sor, value, SOR_DP_LINKCTL0);
2366 tegra_sor_writel(sor, value, SOR_DP_SPARE0);
2370 tegra_sor_writel(sor, value, SOR_SEQ_CTL);
2374 tegra_sor_writel(sor, value, SOR_SEQ_INST(0));
2375 tegra_sor_writel(sor, value, SOR_SEQ_INST(8));
2380 tegra_sor_writel(sor, value, SOR_REFCLK);
2388 tegra_sor_writel(sor, 0x00000000, SOR_XBAR_POL);
2389 tegra_sor_writel(sor, value, SOR_XBAR_CTRL);
2439 tegra_sor_writel(sor, value, SOR_INPUT_CONTROL);
2446 tegra_sor_writel(sor, value, SOR_HDMI_CTRL);
2478 tegra_sor_writel(sor, value, SOR_STATE1);
2483 tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl0);
2500 tegra_sor_writel(sor, value, sor->soc->regs->pll0);
2509 tegra_sor_writel(sor, value, sor->soc->regs->pll1);
2520 tegra_sor_writel(sor, value, sor->soc->regs->pll3);
2526 tegra_sor_writel(sor, value, SOR_LANE_DRIVE_CURRENT0);
2532 tegra_sor_writel(sor, value, SOR_LANE_PREEMPHASIS0);
2538 tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl0);
2543 tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl2);
2548 tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl0);
2589 tegra_sor_writel(sor, value, SOR_STATE1);
2599 tegra_sor_writel(sor, value, sor->soc->regs->head_state0 + dc->pipe);
2605 tegra_sor_writel(sor, value, sor->soc->regs->head_state0 + dc->pipe);
2614 tegra_sor_writel(sor, value, SOR_DP_SPARE0);
2679 tegra_sor_writel(sor, 0, SOR_STATE1);
2691 tegra_sor_writel(sor, value, SOR_STATE1);
2770 tegra_sor_writel(sor, value, sor->soc->regs->pll2);
2776 tegra_sor_writel(sor, value, sor->soc->regs->pll3);
2780 tegra_sor_writel(sor, value, sor->soc->regs->pll0);
2785 tegra_sor_writel(sor, value, sor->soc->regs->pll2);
2792 tegra_sor_writel(sor, value, sor->soc->regs->pll2);
2802 tegra_sor_writel(sor, value, SOR_CLK_CNTRL);
2814 tegra_sor_writel(sor, value, SOR_DP_SPARE0);
2817 tegra_sor_writel(sor, 0, SOR_LVDS);
2825 tegra_sor_writel(sor, value, sor->soc->regs->pll0);
2832 tegra_sor_writel(sor, 0x00000000, SOR_XBAR_POL);
2833 tegra_sor_writel(sor, value, SOR_XBAR_CTRL);
2870 tegra_sor_writel(sor, value, SOR_STATE1);
2875 tegra_sor_writel(sor, value, SOR_DP_LINKCTL0);
2904 tegra_sor_writel(sor, value, SOR_CSTM);
3687 tegra_sor_writel(sor, value, SOR_INT_STATUS);