drm/tegra/sor.c

17 #include <soc/tegra/pmc.h>
411 	const struct tegra_sor_soc *soc;
655 	value = tegra_sor_readl(sor, sor->soc->regs->dp_padctl0);
658 		value &= ~(SOR_DP_PADCTL_PD_TXD(sor->soc->lane_map[3]) |
659 			   SOR_DP_PADCTL_PD_TXD(sor->soc->lane_map[2]));
661 		value |= SOR_DP_PADCTL_PD_TXD(sor->soc->lane_map[3]) |
662 			 SOR_DP_PADCTL_PD_TXD(sor->soc->lane_map[2]);
665 		value &= ~SOR_DP_PADCTL_PD_TXD(sor->soc->lane_map[1]);
667 		value |= SOR_DP_PADCTL_PD_TXD(sor->soc->lane_map[1]);
670 		value &= ~SOR_DP_PADCTL_PD_TXD(sor->soc->lane_map[0]);
672 		value |= SOR_DP_PADCTL_PD_TXD(sor->soc->lane_map[0]);
674 	tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl0);
703 	value = tegra_sor_readl(sor, sor->soc->regs->dp_padctl0);
706 	tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl0);
734 	value = tegra_sor_readl(sor, sor->soc->regs->dp_padctl0);
737 		value &= ~(SOR_DP_PADCTL_CM_TXD(sor->soc->lane_map[3]) |
738 			   SOR_DP_PADCTL_CM_TXD(sor->soc->lane_map[2]));
740 		value |= SOR_DP_PADCTL_CM_TXD(sor->soc->lane_map[3]) |
741 			 SOR_DP_PADCTL_CM_TXD(sor->soc->lane_map[2]);
744 		value &= ~SOR_DP_PADCTL_CM_TXD(sor->soc->lane_map[1]);
746 		value |= SOR_DP_PADCTL_CM_TXD(sor->soc->lane_map[1]);
749 		value &= ~SOR_DP_PADCTL_CM_TXD(sor->soc->lane_map[0]);
751 		value |= SOR_DP_PADCTL_CM_TXD(sor->soc->lane_map[0]);
753 	tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl0);
757 	value = tegra_sor_readl(sor, sor->soc->regs->dp_padctl0);
760 	tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl0);
768 	value = tegra_sor_readl(sor, sor->soc->regs->dp_padctl0);
770 	tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl0);
772 	value = tegra_sor_readl(sor, sor->soc->regs->pll1);
774 	tegra_sor_writel(sor, value, sor->soc->regs->pll1);
779 		value = tegra_sor_readl(sor, sor->soc->regs->pll1);
782 		tegra_sor_writel(sor, value, sor->soc->regs->pll1);
786 		value = tegra_sor_readl(sor, sor->soc->regs->pll1);
793 	value = tegra_sor_readl(sor, sor->soc->regs->pll1);
796 	tegra_sor_writel(sor, value, sor->soc->regs->pll1);
799 	value = tegra_sor_readl(sor, sor->soc->regs->dp_padctl0);
801 	tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl0);
808 	const struct tegra_sor_soc *soc = sor->soc;
816 		u8 shift = sor->soc->lane_map[i] << 3;
818 		voltage_swing |= soc->voltage_swing[pc][vs][pe] << shift;
819 		pre_emphasis |= soc->pre_emphasis[pc][vs][pe] << shift;
820 		post_cursor |= soc->post_cursor[pc][vs][pe] << shift;
822 		if (sor->soc->tx_pu[pc][vs][pe] > tx_pu)
823 			tx_pu = sor->soc->tx_pu[pc][vs][pe];
864 	value = tegra_sor_readl(sor, sor->soc->regs->dp_padctl0);
868 	tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl0);
903 	value = tegra_sor_readl(sor, sor->soc->regs->pll1);
920 	tegra_sor_writel(sor, value, sor->soc->regs->pll1);
1347 	tegra_sor_writel(sor, value, sor->soc->regs->head_state1 + dc->pipe);
1354 	tegra_sor_writel(sor, value, sor->soc->regs->head_state2 + dc->pipe);
1361 	tegra_sor_writel(sor, value, sor->soc->regs->head_state3 + dc->pipe);
1368 	tegra_sor_writel(sor, value, sor->soc->regs->head_state4 + dc->pipe);
1371 	tegra_sor_writel(sor, 0x001, sor->soc->regs->head_state5 + dc->pipe);
1453 	value = tegra_sor_readl(sor, sor->soc->regs->pll2);
1455 	tegra_sor_writel(sor, value, sor->soc->regs->pll2);
1459 	value = tegra_sor_readl(sor, sor->soc->regs->pll0);
1461 	tegra_sor_writel(sor, value, sor->soc->regs->pll0);
1463 	value = tegra_sor_readl(sor, sor->soc->regs->pll2);
1466 	tegra_sor_writel(sor, value, sor->soc->regs->pll2);
2226 	if (!sor->soc->has_nvdisplay)
2285 	value = tegra_sor_readl(sor, sor->soc->regs->pll2);
2287 	tegra_sor_writel(sor, value, sor->soc->regs->pll2);
2291 	value = tegra_sor_readl(sor, sor->soc->regs->pll3);
2293 	tegra_sor_writel(sor, value, sor->soc->regs->pll3);
2295 	value = tegra_sor_readl(sor, sor->soc->regs->pll0);
2298 	tegra_sor_writel(sor, value, sor->soc->regs->pll0);
2300 	value = tegra_sor_readl(sor, sor->soc->regs->pll2);
2302 	tegra_sor_writel(sor, value, sor->soc->regs->pll2);
2306 	value = tegra_sor_readl(sor, sor->soc->regs->pll2);
2309 	tegra_sor_writel(sor, value, sor->soc->regs->pll2);
2313 	value = tegra_sor_readl(sor, sor->soc->regs->dp_padctl0);
2316 	tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl0);
2377 	if (!sor->soc->has_nvdisplay) {
2432 	if (!sor->soc->has_nvdisplay) {
2448 	if (!dc->soc->has_nvdisplay) {
2481 	value = tegra_sor_readl(sor, sor->soc->regs->dp_padctl0);
2483 	tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl0);
2493 	value = tegra_sor_readl(sor, sor->soc->regs->pll0);
2500 	tegra_sor_writel(sor, value, sor->soc->regs->pll0);
2503 	value = tegra_sor_readl(sor, sor->soc->regs->pll1);
2509 	tegra_sor_writel(sor, value, sor->soc->regs->pll1);
2511 	value = tegra_sor_readl(sor, sor->soc->regs->pll3);
2520 	tegra_sor_writel(sor, value, sor->soc->regs->pll3);
2534 	value = tegra_sor_readl(sor, sor->soc->regs->dp_padctl0);
2538 	tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl0);
2540 	value = tegra_sor_readl(sor, sor->soc->regs->dp_padctl2);
2543 	tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl2);
2546 	value = tegra_sor_readl(sor, sor->soc->regs->dp_padctl0);
2548 	tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl0);
2550 	if (!dc->soc->has_nvdisplay) {
2596 	value = tegra_sor_readl(sor, sor->soc->regs->head_state0 + dc->pipe);
2599 	tegra_sor_writel(sor, value, sor->soc->regs->head_state0 + dc->pipe);
2602 	value = tegra_sor_readl(sor, sor->soc->regs->head_state0 + dc->pipe);
2605 	tegra_sor_writel(sor, value, sor->soc->regs->head_state0 + dc->pipe);
2623 	if (!sor->soc->has_nvdisplay)
2630 	if (dc->soc->has_nvdisplay) {
2768 	value = tegra_sor_readl(sor, sor->soc->regs->pll2);
2770 	tegra_sor_writel(sor, value, sor->soc->regs->pll2);
2774 	value = tegra_sor_readl(sor, sor->soc->regs->pll3);
2776 	tegra_sor_writel(sor, value, sor->soc->regs->pll3);
2778 	value = tegra_sor_readl(sor, sor->soc->regs->pll0);
2780 	tegra_sor_writel(sor, value, sor->soc->regs->pll0);
2782 	value = tegra_sor_readl(sor, sor->soc->regs->pll2);
2785 	tegra_sor_writel(sor, value, sor->soc->regs->pll2);
2789 	value = tegra_sor_readl(sor, sor->soc->regs->pll2);
2792 	tegra_sor_writel(sor, value, sor->soc->regs->pll2);
2819 	value = tegra_sor_readl(sor, sor->soc->regs->pll0);
2825 	tegra_sor_writel(sor, value, sor->soc->regs->pll0);
2829 		value |= SOR_XBAR_CTRL_LINK0_XSEL(i, sor->soc->xbar_cfg[i]) |
3054 		} else if (sor->soc->supports_lvds) {
3648 	if (sor->soc->has_nvdisplay) {
3661 		if (!sor->soc->supports_audio)
3671 			sor->xbar_cfg[i] = sor->soc->xbar_cfg[i];
3720 	sor->soc = of_device_get_match_data(&pdev->dev);
3723 	sor->settings = devm_kmemdup(&pdev->dev, sor->soc->settings,
3724 				     sor->soc->num_settings *
3730 	sor->num_settings = sor->soc->num_settings;
3745 		if (sor->soc->supports_hdmi) {
3748 		} else if (sor->soc->supports_lvds) {
3831 	if (sor->soc->supports_hdmi || sor->soc->supports_dp) {