drm/tegra/nvdec.c

69 	int err;
81 	err = falcon_boot(&nvdec->falcon);
82 	if (err < 0)
83 		return err;
85 	err = falcon_wait_idle(&nvdec->falcon);
86 	if (err < 0) {
88 		return err;
96 	int err;
99 	err = readl_poll_timeout(nvdec->regs + NVDEC_FALCON_DEBUGINFO, val, val == 0x0, 10, 100000);
100 	if (err) {
102 		return err;
110 	int err;
112 	err = reset_control_acquire(nvdec->reset);
113 	if (err)
114 		return err;
118 	err = tegra_drm_riscv_boot_bootrom(&nvdec->riscv, nvdec->carveout_base, 1,
120 	if (err) {
125 	err = nvdec_wait_debuginfo(nvdec, "bootloader");
126 	if (err)
129 	err = reset_control_reset(nvdec->reset);
130 	if (err)
135 	err = tegra_drm_riscv_boot_bootrom(&nvdec->riscv, nvdec->carveout_base, 1,
137 	if (err) {
142 	err = nvdec_wait_debuginfo(nvdec, "firmware");
143 	if (err)
149 	return err;
158 	int err;
160 	err = host1x_client_iommu_attach(client);
161 	if (err < 0 && err != -ENODEV) {
162 		dev_err(nvdec->dev, "failed to attach to domain: %d\n", err);
163 		return err;
168 		err = -ENOMEM;
174 		err = -ENOMEM;
178 	err = tegra_drm_register_client(tegra, drm);
179 	if (err < 0)
197 	return err;
206 	int err;
211 	err = tegra_drm_unregister_client(tegra, drm);
212 	if (err < 0)
213 		return err;
251 	int err;
256 	err = falcon_read_firmware(&nvdec->falcon, nvdec->config->firmware);
257 	if (err < 0)
258 		return err;
265 		err = dma_mapping_error(nvdec->dev, iova);
266 		if (err < 0)
267 			return err;
277 	err = falcon_load_firmware(&nvdec->falcon);
278 	if (err < 0)
291 		err = dma_mapping_error(nvdec->dev, phys);
292 		if (err < 0)
306 	return err;
312 	int err;
314 	err = clk_bulk_prepare_enable(nvdec->num_clks, nvdec->clks);
315 	if (err < 0)
316 		return err;
321 		err = nvdec_boot_riscv(nvdec);
322 		if (err < 0)
325 		err = nvdec_load_falcon_firmware(nvdec);
326 		if (err < 0)
329 		err = nvdec_boot_falcon(nvdec);
330 		if (err < 0)
338 	return err;
430 	int err;
433 	err = dma_coerce_mask_and_coherent(dev, *dev->parent->dma_mask);
434 	if (err < 0) {
435 		dev_err(&pdev->dev, "failed to set DMA mask: %d\n", err);
436 		return err;
462 	err = devm_clk_bulk_get(dev, nvdec->num_clks, nvdec->clks);
463 	if (err) {
465 		return err;
468 	err = clk_set_rate(nvdec->clks[0].clk, ULONG_MAX);
469 	if (err < 0) {
471 		return err;
474 	err = of_property_read_u32(dev->of_node, "nvidia,host1x-class", &host_class);
475 	if (err < 0)
488 		err = tegra_mc_get_carveout_info(mc, 1, &nvdec->carveout_base, NULL);
489 		if (err) {
490 			dev_err(dev, "failed to get carveout info: %d\n", err);
491 			return err;
503 		err = tegra_drm_riscv_read_descriptors(&nvdec->riscv);
504 		if (err < 0)
505 			return err;
510 		err = falcon_init(&nvdec->falcon);
511 		if (err < 0)
512 			return err;
529 	err = host1x_client_register(&nvdec->client.base);
530 	if (err < 0) {
531 		dev_err(dev, "failed to register host1x client: %d\n", err);
544 	return err;