Lines Matching refs:dpaux
26 #include "dpaux.h"
76 static inline u32 tegra_dpaux_readl(struct tegra_dpaux *dpaux,
79 u32 value = readl(dpaux->regs + (offset << 2));
81 trace_dpaux_readl(dpaux->dev, offset, value);
86 static inline void tegra_dpaux_writel(struct tegra_dpaux *dpaux,
89 trace_dpaux_writel(dpaux->dev, offset, value);
90 writel(value, dpaux->regs + (offset << 2));
93 static void tegra_dpaux_write_fifo(struct tegra_dpaux *dpaux, const u8 *buffer,
105 tegra_dpaux_writel(dpaux, value, DPAUX_DP_AUXDATA_WRITE(i));
109 static void tegra_dpaux_read_fifo(struct tegra_dpaux *dpaux, u8 *buffer,
118 value = tegra_dpaux_readl(dpaux, DPAUX_DP_AUXDATA_READ(i));
129 struct tegra_dpaux *dpaux = to_dpaux(aux);
196 tegra_dpaux_writel(dpaux, msg->address, DPAUX_DP_AUXADDR);
197 tegra_dpaux_writel(dpaux, value, DPAUX_DP_AUXCTL);
200 tegra_dpaux_write_fifo(dpaux, msg->buffer, msg->size);
205 value = tegra_dpaux_readl(dpaux, DPAUX_DP_AUXCTL);
207 tegra_dpaux_writel(dpaux, value, DPAUX_DP_AUXCTL);
209 status = wait_for_completion_timeout(&dpaux->complete, timeout);
214 value = tegra_dpaux_readl(dpaux, DPAUX_DP_AUXSTAT);
215 tegra_dpaux_writel(dpaux, 0xf00, DPAUX_DP_AUXSTAT);
261 tegra_dpaux_read_fifo(dpaux, msg->buffer, count);
274 struct tegra_dpaux *dpaux = work_to_dpaux(work);
276 if (dpaux->output)
277 drm_helper_hpd_irq_event(dpaux->output->connector.dev);
282 struct tegra_dpaux *dpaux = data;
286 value = tegra_dpaux_readl(dpaux, DPAUX_INTR_AUX);
287 tegra_dpaux_writel(dpaux, value, DPAUX_INTR_AUX);
290 schedule_work(&dpaux->work);
297 complete(&dpaux->complete);
308 static void tegra_dpaux_pad_power_down(struct tegra_dpaux *dpaux)
310 u32 value = tegra_dpaux_readl(dpaux, DPAUX_HYBRID_SPARE);
314 tegra_dpaux_writel(dpaux, value, DPAUX_HYBRID_SPARE);
317 static void tegra_dpaux_pad_power_up(struct tegra_dpaux *dpaux)
319 u32 value = tegra_dpaux_readl(dpaux, DPAUX_HYBRID_SPARE);
323 tegra_dpaux_writel(dpaux, value, DPAUX_HYBRID_SPARE);
326 static int tegra_dpaux_pad_config(struct tegra_dpaux *dpaux, unsigned function)
332 value = DPAUX_HYBRID_PADCTL_AUX_CMH(dpaux->soc->cmh) |
333 DPAUX_HYBRID_PADCTL_AUX_DRVZ(dpaux->soc->drvz) |
334 DPAUX_HYBRID_PADCTL_AUX_DRVI(dpaux->soc->drvi) |
342 DPAUX_HYBRID_PADCTL_AUX_CMH(dpaux->soc->cmh) |
343 DPAUX_HYBRID_PADCTL_AUX_DRVZ(dpaux->soc->drvz) |
344 DPAUX_HYBRID_PADCTL_AUX_DRVI(dpaux->soc->drvi) |
349 tegra_dpaux_pad_power_down(dpaux);
356 tegra_dpaux_writel(dpaux, value, DPAUX_HYBRID_PADCTL);
357 tegra_dpaux_pad_power_up(dpaux);
371 "dpaux-io",
434 struct tegra_dpaux *dpaux = pinctrl_dev_get_drvdata(pinctrl);
436 return tegra_dpaux_pad_config(dpaux, function);
449 struct tegra_dpaux *dpaux;
453 dpaux = devm_kzalloc(&pdev->dev, sizeof(*dpaux), GFP_KERNEL);
454 if (!dpaux)
457 dpaux->soc = of_device_get_match_data(&pdev->dev);
458 INIT_WORK(&dpaux->work, tegra_dpaux_hotplug);
459 init_completion(&dpaux->complete);
460 INIT_LIST_HEAD(&dpaux->list);
461 dpaux->dev = &pdev->dev;
463 dpaux->regs = devm_platform_ioremap_resource(pdev, 0);
464 if (IS_ERR(dpaux->regs))
465 return PTR_ERR(dpaux->regs);
467 dpaux->irq = platform_get_irq(pdev, 0);
468 if (dpaux->irq < 0)
469 return dpaux->irq;
472 dpaux->rst = devm_reset_control_get(&pdev->dev, "dpaux");
473 if (IS_ERR(dpaux->rst)) {
476 PTR_ERR(dpaux->rst));
477 return PTR_ERR(dpaux->rst);
481 dpaux->clk = devm_clk_get(&pdev->dev, NULL);
482 if (IS_ERR(dpaux->clk)) {
484 PTR_ERR(dpaux->clk));
485 return PTR_ERR(dpaux->clk);
488 dpaux->clk_parent = devm_clk_get(&pdev->dev, "parent");
489 if (IS_ERR(dpaux->clk_parent)) {
491 PTR_ERR(dpaux->clk_parent));
492 return PTR_ERR(dpaux->clk_parent);
495 err = clk_set_rate(dpaux->clk_parent, 270000000);
502 dpaux->vdd = devm_regulator_get_optional(&pdev->dev, "vdd");
503 if (IS_ERR(dpaux->vdd)) {
504 if (PTR_ERR(dpaux->vdd) != -ENODEV) {
505 if (PTR_ERR(dpaux->vdd) != -EPROBE_DEFER)
508 PTR_ERR(dpaux->vdd));
510 return PTR_ERR(dpaux->vdd);
513 dpaux->vdd = NULL;
516 platform_set_drvdata(pdev, dpaux);
520 err = devm_request_irq(dpaux->dev, dpaux->irq, tegra_dpaux_irq, 0,
521 dev_name(dpaux->dev), dpaux);
523 dev_err(dpaux->dev, "failed to request IRQ#%u: %d\n",
524 dpaux->irq, err);
528 disable_irq(dpaux->irq);
530 dpaux->aux.transfer = tegra_dpaux_transfer;
531 dpaux->aux.dev = &pdev->dev;
533 drm_dp_aux_init(&dpaux->aux);
543 err = tegra_dpaux_pad_config(dpaux, DPAUX_PADCTL_FUNC_I2C);
548 dpaux->desc.name = dev_name(&pdev->dev);
549 dpaux->desc.pins = tegra_dpaux_pins;
550 dpaux->desc.npins = ARRAY_SIZE(tegra_dpaux_pins);
551 dpaux->desc.pctlops = &tegra_dpaux_pinctrl_ops;
552 dpaux->desc.pmxops = &tegra_dpaux_pinmux_ops;
553 dpaux->desc.owner = THIS_MODULE;
555 dpaux->pinctrl = devm_pinctrl_register(&pdev->dev, &dpaux->desc, dpaux);
556 if (IS_ERR(dpaux->pinctrl)) {
558 err = PTR_ERR(dpaux->pinctrl);
565 tegra_dpaux_writel(dpaux, value, DPAUX_INTR_EN_AUX);
566 tegra_dpaux_writel(dpaux, value, DPAUX_INTR_AUX);
569 list_add_tail(&dpaux->list, &dpaux_list);
572 err = devm_of_dp_aux_populate_ep_devices(&dpaux->aux);
574 dev_err(dpaux->dev, "failed to populate AUX bus: %d\n", err);
588 struct tegra_dpaux *dpaux = platform_get_drvdata(pdev);
590 cancel_work_sync(&dpaux->work);
593 tegra_dpaux_pad_power_down(dpaux);
599 list_del(&dpaux->list);
605 struct tegra_dpaux *dpaux = dev_get_drvdata(dev);
608 if (dpaux->rst) {
609 err = reset_control_assert(dpaux->rst);
618 clk_disable_unprepare(dpaux->clk_parent);
619 clk_disable_unprepare(dpaux->clk);
626 struct tegra_dpaux *dpaux = dev_get_drvdata(dev);
629 err = clk_prepare_enable(dpaux->clk);
635 err = clk_prepare_enable(dpaux->clk_parent);
643 if (dpaux->rst) {
644 err = reset_control_deassert(dpaux->rst);
656 clk_disable_unprepare(dpaux->clk_parent);
658 clk_disable_unprepare(dpaux->clk);
685 { .compatible = "nvidia,tegra194-dpaux", .data = &tegra194_dpaux_soc },
686 { .compatible = "nvidia,tegra186-dpaux", .data = &tegra210_dpaux_soc },
687 { .compatible = "nvidia,tegra210-dpaux", .data = &tegra210_dpaux_soc },
688 { .compatible = "nvidia,tegra124-dpaux", .data = &tegra124_dpaux_soc },
695 .name = "tegra-dpaux",
705 struct tegra_dpaux *dpaux;
709 list_for_each_entry(dpaux, &dpaux_list, list)
710 if (np == dpaux->dev->of_node) {
712 return &dpaux->aux;
722 struct tegra_dpaux *dpaux = to_dpaux(aux);
732 dpaux->output = output;
737 if (dpaux->vdd) {
738 err = regulator_enable(dpaux->vdd);
758 enable_irq(dpaux->irq);
764 struct tegra_dpaux *dpaux = to_dpaux(aux);
769 disable_irq(dpaux->irq);
771 if (dpaux->output->panel) {
774 if (dpaux->vdd) {
775 err = regulator_disable(dpaux->vdd);
794 dpaux->output = NULL;
802 struct tegra_dpaux *dpaux = to_dpaux(aux);
805 value = tegra_dpaux_readl(dpaux, DPAUX_DP_AUXSTAT);
815 struct tegra_dpaux *dpaux = to_dpaux(aux);
817 return tegra_dpaux_pad_config(dpaux, DPAUX_PADCTL_FUNC_AUX);
822 struct tegra_dpaux *dpaux = to_dpaux(aux);
824 tegra_dpaux_pad_power_down(dpaux);