Lines Matching refs:reg
129 u32 reg;
131 reg = readl(tmds->hdmi->base + SUN4I_HDMI_PAD_CTRL1_REG);
132 if (reg & SUN4I_HDMI_PAD_CTRL1_HALVE_CLK)
135 reg = readl(tmds->hdmi->base + SUN4I_HDMI_PLL_CTRL_REG);
136 reg = ((reg >> 4) & 0xf) + tmds->div_offset;
137 if (!reg)
138 reg = 1;
140 return parent_rate / reg;
148 u32 reg;
154 reg = readl(tmds->hdmi->base + SUN4I_HDMI_PAD_CTRL1_REG);
155 reg &= ~SUN4I_HDMI_PAD_CTRL1_HALVE_CLK;
157 reg |= SUN4I_HDMI_PAD_CTRL1_HALVE_CLK;
158 writel(reg, tmds->hdmi->base + SUN4I_HDMI_PAD_CTRL1_REG);
160 reg = readl(tmds->hdmi->base + SUN4I_HDMI_PLL_CTRL_REG);
161 reg &= ~SUN4I_HDMI_PLL_CTRL_DIV_MASK;
162 writel(reg | SUN4I_HDMI_PLL_CTRL_DIV(div - tmds->div_offset),
171 u32 reg;
173 reg = readl(tmds->hdmi->base + SUN4I_HDMI_PLL_DBG0_REG);
174 return ((reg & SUN4I_HDMI_PLL_DBG0_TMDS_PARENT_MASK) >>
181 u32 reg;
186 reg = readl(tmds->hdmi->base + SUN4I_HDMI_PLL_DBG0_REG);
187 reg &= ~SUN4I_HDMI_PLL_DBG0_TMDS_PARENT_MASK;
188 writel(reg | SUN4I_HDMI_PLL_DBG0_TMDS_PARENT(index),