drm/sun4i/sun4i_hdmi_enc.c

40 static int sun4i_hdmi_setup_avi_infoframes(struct sun4i_hdmi *hdmi,
48 						       &hdmi->connector, mode);
61 		writeb(buffer[i], hdmi->base + SUN4I_HDMI_AVI_INFOFRAME_REG(i));
69 	struct sun4i_hdmi *hdmi = drm_encoder_to_sun4i_hdmi(encoder);
74 	val = readl(hdmi->base + SUN4I_HDMI_VID_CTRL_REG);
76 	writel(val, hdmi->base + SUN4I_HDMI_VID_CTRL_REG);
78 	clk_disable_unprepare(hdmi->tmds_clk);
85 	struct sun4i_hdmi *hdmi = drm_encoder_to_sun4i_hdmi(encoder);
86 	struct drm_display_info *display = &hdmi->connector.display_info;
92 	clk_set_rate(hdmi->mod_clk, mode->crtc_clock * 1000);
93 	clk_set_rate(hdmi->tmds_clk, mode->crtc_clock * 1000);
97 	       hdmi->base + SUN4I_HDMI_UNKNOWN_REG);
109 	val = readl(hdmi->base + SUN4I_HDMI_PAD_CTRL1_REG);
111 	val |= hdmi->variant->pad_ctrl1_init_val;
112 	writel(val, hdmi->base + SUN4I_HDMI_PAD_CTRL1_REG);
113 	val = readl(hdmi->base + SUN4I_HDMI_PAD_CTRL1_REG);
118 	       hdmi->base + SUN4I_HDMI_VID_TIMING_ACT_REG);
123 	       hdmi->base + SUN4I_HDMI_VID_TIMING_BP_REG);
128 	       hdmi->base + SUN4I_HDMI_VID_TIMING_FP_REG);
133 	       hdmi->base + SUN4I_HDMI_VID_TIMING_SPW_REG);
142 	writel(val, hdmi->base + SUN4I_HDMI_VID_TIMING_POL_REG);
144 	clk_prepare_enable(hdmi->tmds_clk);
146 	sun4i_hdmi_setup_avi_infoframes(hdmi, mode);
149 	writel(val, hdmi->base + SUN4I_HDMI_PKT_CTRL_REG(0));
155 	writel(val, hdmi->base + SUN4I_HDMI_VID_CTRL_REG);
168 	const struct sun4i_hdmi *hdmi = drm_connector_to_sun4i_hdmi(connector);
179 	rounded_rate = clk_round_rate(hdmi->tmds_clk, clock);
216 	struct sun4i_hdmi *hdmi = drm_connector_to_sun4i_hdmi(connector);
220 	drm_edid = drm_edid_read_ddc(connector, hdmi->ddc_i2c ?: hdmi->i2c);
223 	cec_s_phys_addr(hdmi->cec_adap,
270 	struct sun4i_hdmi *hdmi = drm_connector_to_sun4i_hdmi(connector);
273 	reg = readl(hdmi->base + SUN4I_HDMI_HPD_REG);
275 		cec_phys_addr_invalidate(hdmi->cec_adap);
294 	struct sun4i_hdmi *hdmi = cec_get_drvdata(adap);
296 	return readl(hdmi->base + SUN4I_HDMI_CEC) & SUN4I_HDMI_CEC_RX;
301 	struct sun4i_hdmi *hdmi = cec_get_drvdata(adap);
304 	writel(SUN4I_HDMI_CEC_ENABLE, hdmi->base + SUN4I_HDMI_CEC);
309 	struct sun4i_hdmi *hdmi = cec_get_drvdata(adap);
315 	writel(0, hdmi->base + SUN4I_HDMI_CEC);
502 	struct sun4i_hdmi *hdmi;
506 	hdmi = devm_kzalloc(dev, sizeof(*hdmi), GFP_KERNEL);
507 	if (!hdmi)
509 	dev_set_drvdata(dev, hdmi);
510 	hdmi->dev = dev;
511 	hdmi->drv = drv;
513 	hdmi->variant = of_device_get_match_data(dev);
514 	if (!hdmi->variant)
517 	hdmi->base = devm_platform_ioremap_resource(pdev, 0);
518 	if (IS_ERR(hdmi->base)) {
520 		return PTR_ERR(hdmi->base);
523 	if (hdmi->variant->has_reset_control) {
524 		hdmi->reset = devm_reset_control_get(dev, NULL);
525 		if (IS_ERR(hdmi->reset)) {
527 			return PTR_ERR(hdmi->reset);
530 		ret = reset_control_deassert(hdmi->reset);
537 	hdmi->bus_clk = devm_clk_get(dev, "ahb");
538 	if (IS_ERR(hdmi->bus_clk)) {
540 		ret = PTR_ERR(hdmi->bus_clk);
543 	clk_prepare_enable(hdmi->bus_clk);
545 	hdmi->mod_clk = devm_clk_get(dev, "mod");
546 	if (IS_ERR(hdmi->mod_clk)) {
548 		ret = PTR_ERR(hdmi->mod_clk);
551 	clk_prepare_enable(hdmi->mod_clk);
553 	hdmi->pll0_clk = devm_clk_get(dev, "pll-0");
554 	if (IS_ERR(hdmi->pll0_clk)) {
556 		ret = PTR_ERR(hdmi->pll0_clk);
560 	hdmi->pll1_clk = devm_clk_get(dev, "pll-1");
561 	if (IS_ERR(hdmi->pll1_clk)) {
563 		ret = PTR_ERR(hdmi->pll1_clk);
567 	hdmi->regmap = devm_regmap_init_mmio(dev, hdmi->base,
569 	if (IS_ERR(hdmi->regmap)) {
571 		ret = PTR_ERR(hdmi->regmap);
575 	ret = sun4i_tmds_create(hdmi);
581 	if (hdmi->variant->has_ddc_parent_clk) {
582 		hdmi->ddc_parent_clk = devm_clk_get(dev, "ddc");
583 		if (IS_ERR(hdmi->ddc_parent_clk)) {
585 			ret = PTR_ERR(hdmi->ddc_parent_clk);
589 		hdmi->ddc_parent_clk = hdmi->tmds_clk;
592 	writel(SUN4I_HDMI_CTRL_ENABLE, hdmi->base + SUN4I_HDMI_CTRL_REG);
594 	writel(hdmi->variant->pad_ctrl0_init_val,
595 	       hdmi->base + SUN4I_HDMI_PAD_CTRL0_REG);
597 	reg = readl(hdmi->base + SUN4I_HDMI_PLL_CTRL_REG);
599 	reg |= hdmi->variant->pll_ctrl_init_val;
600 	writel(reg, hdmi->base + SUN4I_HDMI_PLL_CTRL_REG);
602 	ret = sun4i_hdmi_i2c_create(dev, hdmi);
608 	hdmi->ddc_i2c = sun4i_hdmi_get_ddc(dev);
609 	if (IS_ERR(hdmi->ddc_i2c)) {
610 		ret = PTR_ERR(hdmi->ddc_i2c);
612 			hdmi->ddc_i2c = NULL;
617 	drm_encoder_helper_add(&hdmi->encoder,
619 	ret = drm_simple_encoder_init(drm, &hdmi->encoder,
626 	hdmi->encoder.possible_crtcs = drm_of_find_possible_crtcs(drm,
628 	if (!hdmi->encoder.possible_crtcs) {
634 	hdmi->cec_adap = cec_pin_allocate_adapter(&sun4i_hdmi_cec_pin_ops,
635 		hdmi, "sun4i", CEC_CAP_DEFAULTS | CEC_CAP_CONNECTOR_INFO);
636 	ret = PTR_ERR_OR_ZERO(hdmi->cec_adap);
639 	writel(readl(hdmi->base + SUN4I_HDMI_CEC) & ~SUN4I_HDMI_CEC_TX,
640 	       hdmi->base + SUN4I_HDMI_CEC);
643 	drm_connector_helper_add(&hdmi->connector,
645 	ret = drm_connector_init_with_ddc(drm, &hdmi->connector,
648 					  hdmi->ddc_i2c);
654 	cec_fill_conn_info_from_drm(&conn_info, &hdmi->connector);
655 	cec_s_conn_info(hdmi->cec_adap, &conn_info);
658 	hdmi->connector.polled = DRM_CONNECTOR_POLL_CONNECT |
661 	ret = cec_register_adapter(hdmi->cec_adap, dev);
664 	drm_connector_attach_encoder(&hdmi->connector, &hdmi->encoder);
669 	cec_delete_adapter(hdmi->cec_adap);
670 	drm_encoder_cleanup(&hdmi->encoder);
672 	i2c_put_adapter(hdmi->ddc_i2c);
674 	i2c_del_adapter(hdmi->i2c);
676 	clk_disable_unprepare(hdmi->mod_clk);
678 	clk_disable_unprepare(hdmi->bus_clk);
680 	reset_control_assert(hdmi->reset);
687 	struct sun4i_hdmi *hdmi = dev_get_drvdata(dev);
689 	cec_unregister_adapter(hdmi->cec_adap);
690 	i2c_del_adapter(hdmi->i2c);
691 	i2c_put_adapter(hdmi->ddc_i2c);
692 	clk_disable_unprepare(hdmi->mod_clk);
693 	clk_disable_unprepare(hdmi->bus_clk);
712 	{ .compatible = "allwinner,sun4i-a10-hdmi", .data = &sun4i_variant, },
713 	{ .compatible = "allwinner,sun5i-a10s-hdmi", .data = &sun5i_variant, },
714 	{ .compatible = "allwinner,sun6i-a31-hdmi", .data = &sun6i_variant, },
723 		.name		= "sun4i-hdmi",