drm/sun4i/sun4i_backend.c

35 	/* backend <-> TCON muxing selection done in backend */
81 void sun4i_backend_layer_enable(struct sun4i_backend *backend,
94 	regmap_update_bits(backend->engine.regs, SUN4I_BACKEND_MODCTL_REG,
169 int sun4i_backend_update_layer_coord(struct sun4i_backend *backend,
179 	regmap_write(backend->engine.regs, SUN4I_BACKEND_LAYSIZE_REG(layer),
186 	regmap_write(backend->engine.regs, SUN4I_BACKEND_LAYCOOR_REG(layer),
193 static int sun4i_backend_update_yuv_format(struct sun4i_backend *backend,
204 		regmap_write(backend->engine.regs,
212 	regmap_update_bits(backend->engine.regs, SUN4I_BACKEND_ATTCTL_REG0(layer),
245 	regmap_write(backend->engine.regs, SUN4I_BACKEND_IYUVCTL_REG, val);
250 int sun4i_backend_update_layer_formats(struct sun4i_backend *backend,
259 	regmap_update_bits(backend->engine.regs, SUN4I_BACKEND_ATTCTL_REG0(layer),
265 	regmap_update_bits(backend->engine.regs,
272 		return sun4i_backend_update_yuv_format(backend, layer, plane);
280 	regmap_update_bits(backend->engine.regs,
287 int sun4i_backend_update_layer_frontend(struct sun4i_backend *backend,
299 	regmap_update_bits(backend->engine.regs,
304 	regmap_update_bits(backend->engine.regs,
311 static int sun4i_backend_update_yuv_buffer(struct sun4i_backend *backend,
317 	regmap_write(backend->engine.regs, SUN4I_BACKEND_IYUVADD_REG(0), paddr);
320 	regmap_write(backend->engine.regs, SUN4I_BACKEND_IYUVLINEWIDTH_REG(0),
326 int sun4i_backend_update_layer_buffer(struct sun4i_backend *backend,
336 	regmap_write(backend->engine.regs,
345 		return sun4i_backend_update_yuv_buffer(backend, fb, dma_addr);
350 	regmap_write(backend->engine.regs,
357 	regmap_update_bits(backend->engine.regs, SUN4I_BACKEND_LAYFB_H4ADD_REG,
364 int sun4i_backend_update_layer_zpos(struct sun4i_backend *backend, int layer,
374 	regmap_update_bits(backend->engine.regs, SUN4I_BACKEND_ATTCTL_REG0(layer),
383 void sun4i_backend_cleanup_layer(struct sun4i_backend *backend,
386 	regmap_update_bits(backend->engine.regs,
409 	struct sun4i_backend *backend = layer->backend;
413 	if (IS_ERR(backend->frontend))
423 	 * TODO: The backend alone allows 2x and 4x integer scaling, including
425 	 * Use the backend directly instead of the frontend in this case, with
433 	 * Here the format is supported by both the frontend and the backend
434 	 * and no frontend scaling is required, so use the backend directly.
471 	struct sun4i_backend *backend = engine_to_sun4i_backend(engine);
562 	if (backend->quirks->supports_lowest_plane_alpha)
571 	if (!backend->quirks->supports_lowest_plane_alpha &&
610 	struct sun4i_backend *backend = engine_to_sun4i_backend(engine);
611 	struct sun4i_frontend *frontend = backend->frontend;
621 	 * This is due to the fact that the backend will not take into
630 	spin_lock(&backend->frontend_lock);
631 	if (backend->frontend_teardown) {
633 		backend->frontend_teardown = false;
635 	spin_unlock(&backend->frontend_lock);
653 	DRM_DEBUG_DRIVER("Switching display backend interlaced mode %s\n",
658 	struct sun4i_backend *backend = dev_get_drvdata(dev);
661 	backend->sat_reset = devm_reset_control_get(dev, "sat");
662 	if (IS_ERR(backend->sat_reset)) {
664 		return PTR_ERR(backend->sat_reset);
667 	ret = reset_control_deassert(backend->sat_reset);
673 	backend->sat_clk = devm_clk_get(dev, "sat");
674 	if (IS_ERR(backend->sat_clk)) {
676 		ret = PTR_ERR(backend->sat_clk);
680 	ret = clk_prepare_enable(backend->sat_clk);
689 	reset_control_assert(backend->sat_reset);
694 	struct sun4i_backend *backend = dev_get_drvdata(dev);
696 	clk_disable_unprepare(backend->sat_clk);
697 	reset_control_assert(backend->sat_reset);
703  * The display backend can take video output from the display frontend, or
706  * tree with of_graph, and we use it here to figure out which backend, if
784 	struct sun4i_backend *backend;
789 	backend = devm_kzalloc(dev, sizeof(*backend), GFP_KERNEL);
790 	if (!backend)
792 	dev_set_drvdata(dev, backend);
793 	spin_lock_init(&backend->frontend_lock);
808 	backend->engine.node = dev->of_node;
809 	backend->engine.ops = &sun4i_backend_engine_ops;
810 	backend->engine.id = sun4i_backend_of_get_id(dev->of_node);
811 	if (backend->engine.id < 0)
812 		return backend->engine.id;
814 	backend->frontend = sun4i_backend_find_frontend(drv, dev->of_node);
815 	if (IS_ERR(backend->frontend))
822 	backend->reset = devm_reset_control_get(dev, NULL);
823 	if (IS_ERR(backend->reset)) {
825 		return PTR_ERR(backend->reset);
828 	ret = reset_control_deassert(backend->reset);
834 	backend->bus_clk = devm_clk_get(dev, "ahb");
835 	if (IS_ERR(backend->bus_clk)) {
836 		dev_err(dev, "Couldn't get the backend bus clock\n");
837 		ret = PTR_ERR(backend->bus_clk);
840 	clk_prepare_enable(backend->bus_clk);
842 	backend->mod_clk = devm_clk_get(dev, "mod");
843 	if (IS_ERR(backend->mod_clk)) {
844 		dev_err(dev, "Couldn't get the backend module clock\n");
845 		ret = PTR_ERR(backend->mod_clk);
849 	ret = clk_set_rate_exclusive(backend->mod_clk, 300000000);
855 	clk_prepare_enable(backend->mod_clk);
857 	backend->ram_clk = devm_clk_get(dev, "ram");
858 	if (IS_ERR(backend->ram_clk)) {
859 		dev_err(dev, "Couldn't get the backend RAM clock\n");
860 		ret = PTR_ERR(backend->ram_clk);
863 	clk_prepare_enable(backend->ram_clk);
866 				    "allwinner,sun8i-a33-display-backend")) {
874 	backend->engine.regs = devm_regmap_init_mmio(dev, regs,
876 	if (IS_ERR(backend->engine.regs)) {
877 		dev_err(dev, "Couldn't create the backend regmap\n");
878 		return PTR_ERR(backend->engine.regs);
881 	list_add_tail(&backend->engine.list, &drv->engine_list);
884 	 * Many of the backend's layer configuration registers have
892 		regmap_write(backend->engine.regs, i, 0);
895 	regmap_write(backend->engine.regs, SUN4I_BACKEND_REGBUFFCTL_REG,
898 	/* Enable the backend */
899 	regmap_write(backend->engine.regs, SUN4I_BACKEND_MODCTL_REG,
908 		 * and TCONs, so we select the backend with same ID.
916 		regmap_update_bits(backend->engine.regs,
919 				   (backend->engine.id
924 	backend->quirks = quirks;
929 	clk_disable_unprepare(backend->ram_clk);
931 	clk_rate_exclusive_put(backend->mod_clk);
932 	clk_disable_unprepare(backend->mod_clk);
934 	clk_disable_unprepare(backend->bus_clk);
936 	reset_control_assert(backend->reset);
943 	struct sun4i_backend *backend = dev_get_drvdata(dev);
945 	list_del(&backend->engine.list);
948 				    "allwinner,sun8i-a33-display-backend"))
951 	clk_disable_unprepare(backend->ram_clk);
952 	clk_rate_exclusive_put(backend->mod_clk);
953 	clk_disable_unprepare(backend->mod_clk);
954 	clk_disable_unprepare(backend->bus_clk);
955 	reset_control_assert(backend->reset);
996 		.compatible = "allwinner,sun4i-a10-display-backend",
1000 		.compatible = "allwinner,sun5i-a13-display-backend",
1004 		.compatible = "allwinner,sun6i-a31-display-backend",
1008 		.compatible = "allwinner,sun7i-a20-display-backend",
1012 		.compatible = "allwinner,sun8i-a23-display-backend",
1016 		.compatible = "allwinner,sun8i-a33-display-backend",
1020 		.compatible = "allwinner,sun9i-a80-display-backend",
1031 		.name		= "sun4i-backend",