Lines Matching refs:pll_out_khz
246 unsigned int idf, ndiv, odf, pll_in_khz, pll_out_khz;
254 pll_out_khz = mode->clock * bpp / lanes;
258 pll_out_khz = (pll_out_khz * 12) / 10;
260 if (pll_out_khz > dsi->lane_max_kbps) {
261 pll_out_khz = dsi->lane_max_kbps;
264 if (pll_out_khz < dsi->lane_min_kbps) {
265 pll_out_khz = dsi->lane_min_kbps;
273 ret = dsi_pll_get_params(dsi, pll_in_khz, pll_out_khz,
279 pll_out_khz = dsi_pll_get_clkout_khz(pll_in_khz, idf, ndiv, odf);
286 val = 4000000 / pll_out_khz;
296 *lane_mbps = pll_out_khz / 1000;
299 pll_in_khz, pll_out_khz, *lane_mbps);
333 unsigned int idf, ndiv, odf, pll_in_khz, pll_out_khz;
341 pll_out_khz = mode->clock * bpp / lanes;
343 if (pll_out_khz > dsi->lane_max_kbps)
348 pll_out_khz = (pll_out_khz * 12) / 10;
350 if (pll_out_khz < dsi->lane_min_kbps)
359 ret = dsi_pll_get_params(dsi, pll_in_khz, pll_out_khz, &idf, &ndiv, &odf);
371 pll_out_khz = dsi_pll_get_clkout_khz(pll_in_khz, idf, ndiv, odf);
373 px_clock_hz = DIV_ROUND_CLOSEST_ULL(1000ULL * pll_out_khz * lanes, bpp);
404 lane_mbps = pll_out_khz / 1000;