Lines Matching refs:reg_val
463 u32 reg_val;
472 reg_val = ctx->vm.hsync_len << 0 |
475 writel(reg_val, ctx->base + REG_DPI_H_TIMING);
477 reg_val = ctx->vm.vsync_len << 0 |
480 writel(reg_val, ctx->base + REG_DPI_V_TIMING);
751 u32 reg_val, int_mask = 0;
753 reg_val = readl(ctx->base + REG_DPU_INT_STS);
756 if (reg_val & BIT_DPU_INT_ERR) {
762 if (reg_val & BIT_DPU_INT_UPDATE_DONE) {
768 if (reg_val & BIT_DPU_INT_DONE) {
773 if (reg_val & BIT_DPU_INT_VSYNC)
776 writel(reg_val, ctx->base + REG_DPU_INT_CLR);