Lines Matching defs:vop2
34 #include <dt-bindings/soc/rockchip,vop2.h>
141 struct vop2 *vop2;
159 struct vop2 *vop2;
177 struct vop2 {
197 /* physical map length of vop2 register */
252 static void vop2_lock(struct vop2 *vop2)
254 mutex_lock(&vop2->vop2_lock);
257 static void vop2_unlock(struct vop2 *vop2)
259 mutex_unlock(&vop2->vop2_lock);
262 static void vop2_writel(struct vop2 *vop2, u32 offset, u32 v)
264 regmap_write(vop2->map, offset, v);
269 regmap_write(vp->vop2->map, vp->data->offset + offset, v);
272 static u32 vop2_readl(struct vop2 *vop2, u32 offset)
276 regmap_read(vop2->map, offset, &val);
302 struct vop2 *vop2 = vp->vop2;
307 regmap_set_bits(vop2->map, RK3568_REG_CFG_DONE, val);
498 static bool vop2_output_rg_swap(struct vop2 *vop2, u32 bus_format)
500 if (vop2->data->soc_id == 3588) {
548 struct vop2 *vop2 = win->vop2;
557 drm_dbg_kms(vop2->drm, "Unsupported format modifier 0x%llx\n",
702 static void vop2_setup_scale(struct vop2 *vop2, const struct vop2_win *win,
744 drm_dbg(vop2->drm, "%s dst_w[%d] should align as 2 pixel\n",
886 struct vop2 *vop2 = vp->vop2;
888 vop2_writel(vop2, RK3568_VP_INT_CLR(vp->id), irq << 16 | irq);
889 vop2_writel(vop2, RK3568_VP_INT_EN(vp->id), irq << 16 | irq);
894 struct vop2 *vop2 = vp->vop2;
896 vop2_writel(vop2, RK3568_VP_INT_EN(vp->id), irq << 16);
899 static int vop2_core_clks_prepare_enable(struct vop2 *vop2)
903 ret = clk_prepare_enable(vop2->hclk);
905 drm_err(vop2->drm, "failed to enable hclk - %d\n", ret);
909 ret = clk_prepare_enable(vop2->aclk);
911 drm_err(vop2->drm, "failed to enable aclk - %d\n", ret);
915 ret = clk_prepare_enable(vop2->pclk);
917 drm_err(vop2->drm, "failed to enable pclk - %d\n", ret);
923 clk_disable_unprepare(vop2->aclk);
925 clk_disable_unprepare(vop2->hclk);
930 static void rk3588_vop2_power_domain_enable_all(struct vop2 *vop2)
934 pd = vop2_readl(vop2, RK3588_SYS_PD_CTRL);
938 vop2_writel(vop2, RK3588_SYS_PD_CTRL, pd);
941 static void vop2_enable(struct vop2 *vop2)
945 ret = pm_runtime_resume_and_get(vop2->dev);
947 drm_err(vop2->drm, "failed to get pm runtime: %d\n", ret);
951 ret = vop2_core_clks_prepare_enable(vop2);
953 pm_runtime_put_sync(vop2->dev);
957 ret = rockchip_drm_dma_attach_device(vop2->drm, vop2->dev);
959 drm_err(vop2->drm, "failed to attach dma mapping, %d\n", ret);
963 if (vop2->data->soc_id == 3566)
964 vop2_writel(vop2, RK3568_OTP_WIN_EN, 1);
966 if (vop2->data->soc_id == 3588)
967 rk3588_vop2_power_domain_enable_all(vop2);
969 vop2_writel(vop2, RK3568_REG_CFG_DONE, RK3568_REG_CFG_DONE__GLB_CFG_DONE_EN);
975 regmap_clear_bits(vop2->map, RK3568_SYS_AUTO_GATING_CTRL,
978 vop2_writel(vop2, RK3568_SYS0_INT_CLR,
980 vop2_writel(vop2, RK3568_SYS0_INT_EN,
982 vop2_writel(vop2, RK3568_SYS1_INT_CLR,
984 vop2_writel(vop2, RK3568_SYS1_INT_EN,
988 static void vop2_disable(struct vop2 *vop2)
990 rockchip_drm_dma_detach_device(vop2->drm, vop2->dev);
992 pm_runtime_put_sync(vop2->dev);
994 regcache_drop_region(vop2->map, 0, vop2_regmap_config.max_register);
996 clk_disable_unprepare(vop2->pclk);
997 clk_disable_unprepare(vop2->aclk);
998 clk_disable_unprepare(vop2->hclk);
1005 struct vop2 *vop2 = vp->vop2;
1009 vop2_lock(vop2);
1032 drm_info(vop2->drm, "wait for vp%d dsp_hold timeout\n", vp->id);
1038 vop2->enable_count--;
1040 if (!vop2->enable_count)
1041 vop2_disable(vop2);
1043 vop2_unlock(vop2);
1062 struct vop2 *vop2;
1075 vop2 = vp->vop2;
1076 vop2_data = vop2->data;
1097 drm_err(vop2->drm, "Invalid size: %dx%d->%dx%d, min size is 4x4\n",
1106 drm_err(vop2->drm, "Invalid source: %dx%d. max input: %dx%d\n",
1119 drm_err(vop2->drm, "Invalid Source: Yuv format not support odd xpos\n");
1131 struct vop2 *vop2 = win->vop2;
1133 drm_dbg(vop2->drm, "%s disable\n", win->data->name);
1202 struct vop2 *vop2 = win->vop2;
1228 * can't update plane when vop2 is disabled.
1274 drm_err(vop2->drm, "vp%d %s dest->x1[%d] + dsp_w[%d] exceed mode hdisplay[%d]\n",
1285 drm_err(vop2->drm, "vp%d %s dest->y1[%d] + dsp_h[%d] exceed mode vdisplay[%d]\n",
1299 drm_err(vop2->drm, "vp%d %s act_w[%d] MODE 16 == 1\n",
1306 drm_err(vop2->drm, "vp%d %s actual_w[%d] not 4 pixel aligned\n",
1317 drm_dbg(vop2->drm, "vp%d update %s[%dx%d->%dx%d@%dx%d] fmt[%p4cc_%s] addr[%pad]\n",
1344 drm_err(vop2->drm, "vp%d %s stride[%d] not 64 pixel aligned\n",
1372 if (vop2->data->soc_id == 3566 || vop2->data->soc_id == 3568)
1421 vop2_setup_scale(vop2, win, actual_w, actual_h, dsp_w, dsp_h, fb->format->format);
1534 vop2_writel(vp->vop2, RK3568_VP_BG_MIX_CTRL(vp->id),
1576 struct vop2 *vop2 = vp->vop2;
1580 die = vop2_readl(vop2, RK3568_DSP_IF_EN);
1581 dip = vop2_readl(vop2, RK3568_DSP_IF_POL);
1591 regmap_write(vop2->sys_grf, RK3568_GRF_VO_CON1, BIT(3 + 16) | BIT(3));
1593 regmap_write(vop2->sys_grf, RK3568_GRF_VO_CON1, BIT(3 + 16));
1638 drm_err(vop2->drm, "Invalid interface id %d on vp%d\n", id, vp->id);
1644 vop2_writel(vop2, RK3568_DSP_IF_EN, die);
1645 vop2_writel(vop2, RK3568_DSP_IF_POL, dip);
1676 struct vop2 *vop2 = vp->vop2;
1726 drm_err(vop2->drm, "DP dclk_out_rate out of range, dclk_out_rate: %ld KHZ\n",
1743 drm_err(vop2->drm, "MIPI dclk out of range, dclk_out_rate: %ld KHZ\n",
1762 drm_dbg(vop2->drm, "dclk: %ld, pixclk_div: %d, dclk_div: %d\n",
1796 struct vop2 *vop2 = vp->vop2;
1809 die = vop2_readl(vop2, RK3568_DSP_IF_EN);
1810 dip = vop2_readl(vop2, RK3568_DSP_IF_POL);
1811 div = vop2_readl(vop2, RK3568_DSP_IF_CTRL);
1823 regmap_write(vop2->vop_grf, RK3588_GRF_VOP_CON2, HIWORD_UPDATE(1, 1, 1));
1824 regmap_write(vop2->vo1_grf, RK3588_GRF_VO1_CON0, HIWORD_UPDATE(val, 6, 5));
1835 regmap_write(vop2->vop_grf, RK3588_GRF_VOP_CON2, HIWORD_UPDATE(1, 4, 4));
1836 regmap_write(vop2->vo1_grf, RK3588_GRF_VO1_CON0, HIWORD_UPDATE(val, 8, 7));
1846 regmap_write(vop2->vop_grf, RK3588_GRF_VOP_CON2, HIWORD_UPDATE(1, 0, 0));
1856 regmap_write(vop2->vop_grf, RK3588_GRF_VOP_CON2, HIWORD_UPDATE(1, 3, 3));
1889 drm_err(vop2->drm, "Invalid interface id %d on vp%d\n", id, vp->id);
1896 vop2_writel(vop2, RK3568_DSP_IF_EN, die);
1897 vop2_writel(vop2, RK3568_DSP_IF_CTRL, div);
1898 vop2_writel(vop2, RK3568_DSP_IF_POL, dip);
1905 struct vop2 *vop2 = vp->vop2;
1907 if (vop2->data->soc_id == 3566 || vop2->data->soc_id == 3568)
1909 else if (vop2->data->soc_id == 3588)
1924 struct vop2 *vop2 = vp->vop2;
1925 const struct vop2_data *vop2_data = vop2->data;
1948 drm_dbg(vop2->drm, "Update mode to %dx%d%s%d, type: %d for vp%d\n",
1952 vop2_lock(vop2);
1956 drm_err(vop2->drm, "failed to enable dclk for video port%d - %d\n",
1958 vop2_unlock(vop2);
1962 if (!vop2->enable_count)
1963 vop2_enable(vop2);
1965 vop2->enable_count++;
1991 vop2_unlock(vop2);
2005 if (vop2_output_rg_swap(vop2, vcstate->bus_format))
2040 vop2_writel(vop2, RK3568_VP_LINE_FLAG(vp->id),
2062 vop2_unlock(vop2);
2146 static int vop2_find_start_mixer_id_for_vp(struct vop2 *vop2, u8 port_id)
2153 vp = &vop2->vps[i];
2160 static void vop2_setup_cluster_alpha(struct vop2 *vop2, struct vop2_win *main_win)
2188 vop2_writel(vop2, RK3568_CLUSTER0_MIX_SRC_COLOR_CTRL + offset,
2190 vop2_writel(vop2, RK3568_CLUSTER0_MIX_DST_COLOR_CTRL + offset,
2192 vop2_writel(vop2, RK3568_CLUSTER0_MIX_SRC_ALPHA_CTRL + offset,
2194 vop2_writel(vop2, RK3568_CLUSTER0_MIX_DST_ALPHA_CTRL + offset,
2200 struct vop2 *vop2 = vp->vop2;
2212 mixer_id = vop2_find_start_mixer_id_for_vp(vop2, vp->id);
2271 vop2_writel(vop2, RK3568_MIX0_SRC_COLOR_CTRL + offset,
2273 vop2_writel(vop2, RK3568_MIX0_DST_COLOR_CTRL + offset,
2275 vop2_writel(vop2, RK3568_MIX0_SRC_ALPHA_CTRL + offset,
2277 vop2_writel(vop2, RK3568_MIX0_DST_ALPHA_CTRL + offset,
2291 vop2_writel(vop2, RK3568_HDR0_SRC_COLOR_CTRL,
2293 vop2_writel(vop2, RK3568_HDR0_DST_COLOR_CTRL,
2295 vop2_writel(vop2, RK3568_HDR0_SRC_ALPHA_CTRL,
2297 vop2_writel(vop2, RK3568_HDR0_DST_ALPHA_CTRL,
2300 vop2_writel(vop2, RK3568_HDR0_SRC_COLOR_CTRL, 0);
2307 struct vop2 *vop2 = vp->vop2;
2314 struct vop2_video_port *vp0 = &vop2->vps[0];
2315 struct vop2_video_port *vp1 = &vop2->vps[1];
2316 struct vop2_video_port *vp2 = &vop2->vps[2];
2319 ovl_ctrl = vop2_readl(vop2, RK3568_OVL_CTRL);
2326 vop2_writel(vop2, RK3568_OVL_CTRL, ovl_ctrl);
2328 port_sel = vop2_readl(vop2, RK3568_OVL_PORT_SEL);
2349 layer_sel = vop2_readl(vop2, RK3568_OVL_LAYER_SEL);
2353 ofs += vop2->vps[i].nlayers;
2415 vop2_writel(vop2, RK3568_OVL_LAYER_SEL, layer_sel);
2416 vop2_writel(vop2, RK3568_OVL_PORT_SEL, port_sel);
2419 static void vop2_setup_dly_for_windows(struct vop2 *vop2)
2425 for (i = 0; i < vop2->data->win_size; i++) {
2428 win = &vop2->win[i];
2455 vop2_writel(vop2, RK3568_CLUSTER_DLY_NUM, cdly);
2456 vop2_writel(vop2, RK3568_SMART_DLY_NUM, sdly);
2463 struct vop2 *vop2 = vp->vop2;
2476 vop2_setup_cluster_alpha(vop2, win);
2484 vop2_setup_dly_for_windows(vop2);
2569 struct vop2 *vop2 = data;
2570 const struct vop2_data *vop2_data = vop2->data;
2577 * vop2-device is disabled the irq has to be targeted at the iommu.
2579 if (!pm_runtime_get_if_in_use(vop2->dev))
2583 struct vop2_video_port *vp = &vop2->vps[i];
2587 irqs = vop2_readl(vop2, RK3568_VP_INT_STATUS(vp->id));
2588 vop2_writel(vop2, RK3568_VP_INT_CLR(vp->id), irqs << 16 | irqs);
2599 u32 val = vop2_readl(vop2, RK3568_REG_CFG_DONE);
2613 drm_err_ratelimited(vop2->drm,
2620 axi_irqs[0] = vop2_readl(vop2, RK3568_SYS0_INT_STATUS);
2621 vop2_writel(vop2, RK3568_SYS0_INT_CLR, axi_irqs[0] << 16 | axi_irqs[0]);
2622 axi_irqs[1] = vop2_readl(vop2, RK3568_SYS1_INT_STATUS);
2623 vop2_writel(vop2, RK3568_SYS1_INT_CLR, axi_irqs[1] << 16 | axi_irqs[1]);
2627 drm_err_ratelimited(vop2->drm, "BUS_ERROR irq err\n");
2632 pm_runtime_put(vop2->dev);
2637 static int vop2_plane_init(struct vop2 *vop2, struct vop2_win *win,
2646 ret = drm_universal_plane_init(vop2->drm, &win->base, possible_crtcs,
2652 drm_err(vop2->drm, "failed to initialize plane %d\n", ret);
2665 vop2->registered_num_wins - 1);
2670 static struct vop2_video_port *find_vp_without_primary(struct vop2 *vop2)
2674 for (i = 0; i < vop2->data->nr_vps; i++) {
2675 struct vop2_video_port *vp = &vop2->vps[i];
2688 static int vop2_create_crtcs(struct vop2 *vop2)
2690 const struct vop2_data *vop2_data = vop2->data;
2691 struct drm_device *drm = vop2->drm;
2692 struct device *dev = vop2->dev;
2705 vp = &vop2->vps[i];
2706 vp->vop2 = vop2;
2711 vp->dclk = devm_clk_get(vop2->dev, dclk_name);
2713 drm_err(vop2->drm, "failed to get %s\n", dclk_name);
2719 drm_dbg(vop2->drm, "%s: No remote for vp%d\n", __func__, i);
2726 drm_err(vop2->drm, "no port node found for video_port%d\n", i);
2735 for (i = 0; i < vop2->registered_num_wins; i++) {
2736 struct vop2_win *win = &vop2->win[i];
2739 if (vop2->data->soc_id == 3566) {
2754 vp = find_vp_without_primary(vop2);
2768 ret = vop2_plane_init(vop2, win, possible_crtcs);
2770 drm_err(vop2->drm, "failed to init plane %s: %d\n",
2777 vp = &vop2->vps[i];
2788 drm_err(vop2->drm, "crtc init for video_port%d failed\n", i);
2802 for (i = 0; i < vop2->data->nr_vps; i++) {
2803 struct vop2_video_port *vp = &vop2->vps[i];
2812 static void vop2_destroy_crtcs(struct vop2 *vop2)
2814 struct drm_device *drm = vop2->drm;
2833 static int vop2_find_rgb_encoder(struct vop2 *vop2)
2835 struct device_node *node = vop2->dev->of_node;
2839 for (i = 0; i < vop2->data->nr_vps; i++) {
2918 struct vop2 *vop2 = win->vop2;
2931 ret = devm_regmap_field_bulk_alloc(vop2->dev, vop2->map, win->reg,
3002 struct vop2 *vop2 = win->vop2;
3015 ret = devm_regmap_field_bulk_alloc(vop2->dev, vop2->map, win->reg,
3024 static int vop2_win_init(struct vop2 *vop2)
3026 const struct vop2_data *vop2_data = vop2->data;
3033 win = &vop2->win[i];
3038 win->vop2 = vop2;
3047 vop2->registered_num_wins = vop2_data->win_size;
3072 .name = "vop2",
3082 struct vop2 *vop2;
3091 /* Allocate vop2 struct and its vop2_win array */
3092 alloc_size = struct_size(vop2, win, vop2_data->win_size);
3093 vop2 = devm_kzalloc(dev, alloc_size, GFP_KERNEL);
3094 if (!vop2)
3097 vop2->dev = dev;
3098 vop2->data = vop2_data;
3099 vop2->drm = drm;
3101 dev_set_drvdata(dev, vop2);
3105 drm_err(vop2->drm, "failed to get vop2 register byname\n");
3109 vop2->regs = devm_ioremap_resource(dev, res);
3110 if (IS_ERR(vop2->regs))
3111 return PTR_ERR(vop2->regs);
3112 vop2->len = resource_size(res);
3114 vop2->map = devm_regmap_init_mmio(dev, vop2->regs, &vop2_regmap_config);
3115 if (IS_ERR(vop2->map))
3116 return PTR_ERR(vop2->map);
3118 ret = vop2_win_init(vop2);
3124 vop2->lut_regs = devm_ioremap_resource(dev, res);
3125 if (IS_ERR(vop2->lut_regs))
3126 return PTR_ERR(vop2->lut_regs);
3129 vop2->sys_grf = syscon_regmap_lookup_by_phandle(dev->of_node, "rockchip,grf");
3130 if (IS_ERR(vop2->sys_grf))
3131 return dev_err_probe(dev, PTR_ERR(vop2->sys_grf), "cannot get sys_grf");
3135 vop2->vop_grf = syscon_regmap_lookup_by_phandle(dev->of_node, "rockchip,vop-grf");
3136 if (IS_ERR(vop2->vop_grf))
3137 return dev_err_probe(dev, PTR_ERR(vop2->vop_grf), "cannot get vop_grf");
3141 vop2->vo1_grf = syscon_regmap_lookup_by_phandle(dev->of_node, "rockchip,vo1-grf");
3142 if (IS_ERR(vop2->vo1_grf))
3143 return dev_err_probe(dev, PTR_ERR(vop2->vo1_grf), "cannot get vo1_grf");
3147 vop2->sys_pmu = syscon_regmap_lookup_by_phandle(dev->of_node, "rockchip,pmu");
3148 if (IS_ERR(vop2->sys_pmu))
3149 return dev_err_probe(dev, PTR_ERR(vop2->sys_pmu), "cannot get sys_pmu");
3152 vop2->hclk = devm_clk_get(vop2->dev, "hclk");
3153 if (IS_ERR(vop2->hclk)) {
3154 drm_err(vop2->drm, "failed to get hclk source\n");
3155 return PTR_ERR(vop2->hclk);
3158 vop2->aclk = devm_clk_get(vop2->dev, "aclk");
3159 if (IS_ERR(vop2->aclk)) {
3160 drm_err(vop2->drm, "failed to get aclk source\n");
3161 return PTR_ERR(vop2->aclk);
3164 vop2->pclk = devm_clk_get_optional(vop2->dev, "pclk_vop");
3165 if (IS_ERR(vop2->pclk)) {
3166 drm_err(vop2->drm, "failed to get pclk source\n");
3167 return PTR_ERR(vop2->pclk);
3170 vop2->irq = platform_get_irq(pdev, 0);
3171 if (vop2->irq < 0) {
3172 drm_err(vop2->drm, "cannot find irq for vop2\n");
3173 return vop2->irq;
3176 mutex_init(&vop2->vop2_lock);
3178 ret = devm_request_irq(dev, vop2->irq, vop2_isr, IRQF_SHARED, dev_name(dev), vop2);
3182 ret = vop2_create_crtcs(vop2);
3186 ret = vop2_find_rgb_encoder(vop2);
3188 vop2->rgb = rockchip_rgb_init(dev, &vop2->vps[ret].crtc,
3189 vop2->drm, ret);
3190 if (IS_ERR(vop2->rgb)) {
3191 if (PTR_ERR(vop2->rgb) == -EPROBE_DEFER) {
3192 ret = PTR_ERR(vop2->rgb);
3195 vop2->rgb = NULL;
3199 rockchip_drm_dma_init_device(vop2->drm, vop2->dev);
3206 vop2_destroy_crtcs(vop2);
3213 struct vop2 *vop2 = dev_get_drvdata(dev);
3217 if (vop2->rgb)
3218 rockchip_rgb_fini(vop2->rgb);
3220 vop2_destroy_crtcs(vop2);