drm/rockchip/dw-mipi-dsi-rockchip.c

205 #define HIWORD_UPDATE(val, mask)	(val | (mask) << 16)
1482 		.lcdsel_big = HIWORD_UPDATE(0, PX30_DSI_LCDC_SEL),
1483 		.lcdsel_lit = HIWORD_UPDATE(PX30_DSI_LCDC_SEL,
1487 		.lanecfg1 = HIWORD_UPDATE(0, PX30_DSI_TURNDISABLE |
1500 		.lcdsel_big = HIWORD_UPDATE(0, RK3288_DSI0_LCDC_SEL),
1501 		.lcdsel_lit = HIWORD_UPDATE(RK3288_DSI0_LCDC_SEL, RK3288_DSI0_LCDC_SEL),
1508 		.lcdsel_big = HIWORD_UPDATE(0, RK3288_DSI1_LCDC_SEL),
1509 		.lcdsel_lit = HIWORD_UPDATE(RK3288_DSI1_LCDC_SEL, RK3288_DSI1_LCDC_SEL),
1525 		     HIWORD_UPDATE(0, RK3399_TXRX_SRC_SEL_ISP0));
1527 		     HIWORD_UPDATE(0, RK3399_TXRX_MASTERSLAVEZ));
1529 		     HIWORD_UPDATE(0, RK3399_TXRX_BASEDIR));
1531 		     HIWORD_UPDATE(0, RK3399_DSI1_ENABLE));
1545 		     HIWORD_UPDATE(0, RK3399_TXRX_MASTERSLAVEZ));
1547 		     HIWORD_UPDATE(RK3399_TXRX_BASEDIR, RK3399_TXRX_BASEDIR));
1550 		     HIWORD_UPDATE(0, RK3399_DSI1_FORCERXMODE));
1552 		     HIWORD_UPDATE(0, RK3399_DSI1_FORCETXSTOPMODE));
1556 		     HIWORD_UPDATE(0, RK3399_TXRX_TURNREQUEST));
1558 		     HIWORD_UPDATE(RK3399_DSI1_TURNDISABLE,
1567 		     HIWORD_UPDATE(GENMASK(dsi->dphy_config.lanes - 1, 0),
1580 		     HIWORD_UPDATE(0, RK3399_DSI1_ENABLE));
1589 		.lcdsel_big = HIWORD_UPDATE(0, RK3399_DSI0_LCDC_SEL),
1590 		.lcdsel_lit = HIWORD_UPDATE(RK3399_DSI0_LCDC_SEL,
1594 		.lanecfg1 = HIWORD_UPDATE(0, RK3399_DSI0_TURNREQUEST |
1605 		.lcdsel_big = HIWORD_UPDATE(0, RK3399_DSI1_LCDC_SEL),
1606 		.lcdsel_lit = HIWORD_UPDATE(RK3399_DSI1_LCDC_SEL,
1610 		.lanecfg1 = HIWORD_UPDATE(0, RK3399_DSI1_TURNDISABLE |
1616 		.lanecfg2 = HIWORD_UPDATE(RK3399_TXRX_MASTERSLAVEZ |
1623 		.enable = HIWORD_UPDATE(RK3399_DSI1_ENABLE, RK3399_DSI1_ENABLE),
1639 		.lanecfg1 = HIWORD_UPDATE(0, RK3568_DSI0_SKEWCALHS |
1648 		.lanecfg1 = HIWORD_UPDATE(0, RK3568_DSI1_SKEWCALHS |
1661 		.lanecfg1 = HIWORD_UPDATE(0, RV1126_DSI_TURNDISABLE |