renesas/rz-du/rzg2l_du_crtc.c

69 	struct rzg2l_du_device *rcdu = rcrtc->dev;
92 	writel(ditr0, rcdu->mmio + DU_DITR0);
93 	writel(ditr1, rcdu->mmio + DU_DITR1);
94 	writel(ditr2, rcdu->mmio + DU_DITR2);
95 	writel(ditr3, rcdu->mmio + DU_DITR3);
96 	writel(ditr4, rcdu->mmio + DU_DITR4);
97 	writel(pbcr0, rcdu->mmio + DU_PBCR0);
100 	writel(DU_MCR1_PB_AUTOCLR, rcdu->mmio + DU_MCR1);
144 	struct rzg2l_du_device *rcdu = rcrtc->dev;
151 	dev_warn(rcdu->dev, "page flip timeout\n");
219 	struct rzg2l_du_device *rcdu = rcrtc->dev;
221 	writel(start ? DU_MCR0_DI_EN : 0, rcdu->mmio + DU_MCR0);
376 int rzg2l_du_crtc_create(struct rzg2l_du_device *rcdu)
378 	struct rzg2l_du_crtc *rcrtc = &rcdu->crtcs[0];
383 	rcrtc->rstc = devm_reset_control_get_shared(rcdu->dev, NULL);
385 		dev_err(rcdu->dev, "can't get cpg reset\n");
389 	rcrtc->rzg2l_clocks.aclk = devm_clk_get(rcdu->dev, "aclk");
391 		dev_err(rcdu->dev, "no axi clock for DU\n");
395 	rcrtc->rzg2l_clocks.pclk = devm_clk_get(rcdu->dev, "pclk");
397 		dev_err(rcdu->dev, "no peripheral clock for DU\n");
401 	rcrtc->rzg2l_clocks.dclk = devm_clk_get(rcdu->dev, "vclk");
403 		dev_err(rcdu->dev, "no video clock for DU\n");
408 	rcrtc->dev = rcdu;
414 	ret = drmm_crtc_init_with_planes(&rcdu->ddev, crtc, primary, NULL,