Lines Matching defs:output
146 unsigned long output;
168 * The clock output by the PLL is then further divided by a programmable
181 * clock for the DU RGB output, without using the LVDS encoder.
222 * The output frequency is limited to 1039.5 MHz,
261 output = fin * pll->pll_n / pll->pll_m / (1 << pll->pll_e)
263 error = (long)(output - target) * 10000 / (long)target;
267 clk, fin, output, target, error / 100,
488 /* Turn the output on. */
610 * We could clear the LVRES bit already to disable the LVDS output, but
709 * odd pixels than we need to enable vertical stripe output.
762 * to the output ports of both encoders, therefore leave it like this
798 * used for the DPAD output even when the LVDS output is not connected.