drm/radeon/vce_v2_0.c

41 	u32 tmp;
44 		tmp = RREG32(VCE_CLOCK_GATING_B);
45 		tmp |= 0xe70000;
46 		WREG32(VCE_CLOCK_GATING_B, tmp);
48 		tmp = RREG32(VCE_UENC_CLOCK_GATING);
49 		tmp |= 0xff000000;
50 		WREG32(VCE_UENC_CLOCK_GATING, tmp);
52 		tmp = RREG32(VCE_UENC_REG_CLOCK_GATING);
53 		tmp &= ~0x3fc;
54 		WREG32(VCE_UENC_REG_CLOCK_GATING, tmp);
58 		tmp = RREG32(VCE_CLOCK_GATING_B);
59 		tmp |= 0xe7;
60 		tmp &= ~0xe70000;
61 		WREG32(VCE_CLOCK_GATING_B, tmp);
63 		tmp = RREG32(VCE_UENC_CLOCK_GATING);
64 		tmp |= 0x1fe000;
65 		tmp &= ~0xff000000;
66 		WREG32(VCE_UENC_CLOCK_GATING, tmp);
68 		tmp = RREG32(VCE_UENC_REG_CLOCK_GATING);
69 		tmp |= 0x3fc;
70 		WREG32(VCE_UENC_REG_CLOCK_GATING, tmp);
76 	u32 orig, tmp;
78 	tmp = RREG32(VCE_CLOCK_GATING_B);
79 	tmp &= ~0x00060006;
81 		tmp |= 0xe10000;
83 		tmp |= 0xe1;
84 		tmp &= ~0xe10000;
86 	WREG32(VCE_CLOCK_GATING_B, tmp);
88 	orig = tmp = RREG32(VCE_UENC_CLOCK_GATING);
89 	tmp &= ~0x1fe000;
90 	tmp &= ~0xff000000;
91 	if (tmp != orig)
92 		WREG32(VCE_UENC_CLOCK_GATING, tmp);
94 	orig = tmp = RREG32(VCE_UENC_REG_CLOCK_GATING);
95 	tmp &= ~0x3fc;
96 	if (tmp != orig)
97 		WREG32(VCE_UENC_REG_CLOCK_GATING, tmp);
133 	u32 tmp;
135 	tmp = RREG32(VCE_CLOCK_GATING_A);
136 	tmp &= ~(CGC_CLK_GATE_DLY_TIMER_MASK | CGC_CLK_GATER_OFF_DLY_TIMER_MASK);
137 	tmp |= (CGC_CLK_GATE_DLY_TIMER(0) | CGC_CLK_GATER_OFF_DLY_TIMER(4));
138 	tmp |= CGC_UENC_WAIT_AWAKE;
139 	WREG32(VCE_CLOCK_GATING_A, tmp);
141 	tmp = RREG32(VCE_UENC_CLOCK_GATING);
142 	tmp &= ~(CLOCK_ON_DELAY_MASK | CLOCK_OFF_DELAY_MASK);
143 	tmp |= (CLOCK_ON_DELAY(0) | CLOCK_OFF_DELAY(4));
144 	WREG32(VCE_UENC_CLOCK_GATING, tmp);
146 	tmp = RREG32(VCE_CLOCK_GATING_B);
147 	tmp |= 0x10;
148 	tmp &= ~0x100000;
149 	WREG32(VCE_CLOCK_GATING_B, tmp);