drm/radeon/smu7_fusion.h

45     uint8_t         DisplayPhy1Config;
46     uint8_t         DisplayPhy2Config;
47     uint8_t         DisplayPhy3Config;
48     uint8_t         DisplayPhy4Config;
50     uint8_t         DisplayPhy5Config;
51     uint8_t         DisplayPhy6Config;
52     uint8_t         DisplayPhy7Config;
53     uint8_t         DisplayPhy8Config;
59     uint8_t         SClkDpmEnabledLevels;
60     uint8_t         MClkDpmEnabledLevels;
61     uint8_t         LClkDpmEnabledLevels;
62     uint8_t         PCIeDpmEnabledLevels;
64     uint8_t         UVDDpmEnabledLevels;
65     uint8_t         SAMUDpmEnabledLevels;
66     uint8_t         ACPDpmEnabledLevels;
67     uint8_t         VCEDpmEnabledLevels;
87     uint8_t     Vid;
88     uint8_t     VidOffset;
91     uint8_t     PowerThrottle;
92     uint8_t     GnbSlow;
93     uint8_t     ForceNbPs1;
94     uint8_t     SclkDid;
96     uint8_t     DisplayWatermark;
97     uint8_t     EnabledForActivity;
98     uint8_t     EnabledForThrottle;
99     uint8_t     UpH;
101     uint8_t     DownH;
102     uint8_t     VoltageDownH;
103     uint8_t     DeepSleepDivId;
105     uint8_t     ClkBypassCntl;
113     uint8_t     EnabledForActivity;
114     uint8_t     LclkDid;
115     uint8_t     Vid;
116     uint8_t     VoltageDownH;
121     uint8_t     UpH;
122     uint8_t     DownH;
126     uint8_t     ActivityLevel;
127     uint8_t     EnabledForThrottle;
129     uint8_t     ClkBypassCntl;
131     uint8_t     padding;
141     uint8_t  VclkDivider;
142     uint8_t  DclkDivider;
144     uint8_t     VClkBypassCntl;
145     uint8_t     DClkBypassCntl;
147     uint8_t     padding[2];
157     uint8_t  Divider;
158     uint8_t  ClkBypassCntl;
168     uint8_t     SclkDid;
169     uint8_t     GnbSlow;
170     uint8_t     ForceNbPs1;
171     uint8_t     DisplayWatermark;
172     uint8_t     DeepSleepDivId;
173     uint8_t     padding[3];
179     uint8_t DpmXNbPsHi;
180     uint8_t DpmXNbPsLo;
181     uint8_t Dpm0PgNbPsHi;
182     uint8_t Dpm0PgNbPsLo;
183     uint8_t EnablePsi1;
184     uint8_t SkipDPM0;
185     uint8_t SkipPG;
186     uint8_t Hysteresis;
187     uint8_t EnableDpmPstatePoll;
188     uint8_t padding[3];
201     uint8_t  DisplayWatermark;
202     uint8_t  McArbIndex;
215     uint8_t                            GraphicsDpmLevelCount;
216     uint8_t                            GIOLevelCount;
217     uint8_t                            UvdLevelCount;
218     uint8_t                            VceLevelCount;
220     uint8_t                            AcpLevelCount;
221     uint8_t                            SamuLevelCount;
231     uint8_t                           UvdBootLevel;
232     uint8_t                           VceBootLevel;
233     uint8_t                           AcpBootLevel;
234     uint8_t                           SamuBootLevel;
235     uint8_t                           UVDInterval;
236     uint8_t                           VCEInterval;
237     uint8_t                           ACPInterval;
238     uint8_t                           SAMUInterval;
240     uint8_t                           GraphicsBootLevel;
241     uint8_t                           GraphicsInterval;
242     uint8_t                           GraphicsThermThrottleEnable;
243     uint8_t                           GraphicsVoltageChangeEnable;
245     uint8_t                           GraphicsClkSlowEnable;
246     uint8_t                           GraphicsClkSlowDivider;
268     uint8_t                           Enable;
269     uint8_t                           GIOVoltageChangeEnable;
270     uint8_t                           GIOBootLevel;
271     uint8_t                           padding;
272     uint8_t                           padding1[2];
273     uint8_t                           TargetState;
274     uint8_t                           CurrenttState;
275     uint8_t                           ThrottleOnHtc;
276     uint8_t                           ThermThrottleStatus;
277     uint8_t                           ThermThrottleTempSelect;
278     uint8_t                           ThermThrottleEnable;