Lines Matching defs:gb_addr_config
3071 u32 gb_addr_config = 0;
3094 gb_addr_config = TAHITI_GB_ADDR_CONFIG_GOLDEN;
3111 gb_addr_config = TAHITI_GB_ADDR_CONFIG_GOLDEN;
3129 gb_addr_config = VERDE_GB_ADDR_CONFIG_GOLDEN;
3146 gb_addr_config = VERDE_GB_ADDR_CONFIG_GOLDEN;
3163 gb_addr_config = HAINAN_GB_ADDR_CONFIG_GOLDEN;
3199 gb_addr_config &= ~ROW_SIZE_MASK;
3203 gb_addr_config |= ROW_SIZE(0);
3206 gb_addr_config |= ROW_SIZE(1);
3209 gb_addr_config |= ROW_SIZE(2);
3213 /* setup tiling info dword. gb_addr_config is not adequate since it does
3250 ((gb_addr_config & PIPE_INTERLEAVE_SIZE_MASK) >> PIPE_INTERLEAVE_SIZE_SHIFT) << 8;
3252 ((gb_addr_config & ROW_SIZE_MASK) >> ROW_SIZE_SHIFT) << 12;
3254 WREG32(GB_ADDR_CONFIG, gb_addr_config);
3255 WREG32(DMIF_ADDR_CONFIG, gb_addr_config);
3256 WREG32(DMIF_ADDR_CALC, gb_addr_config);
3257 WREG32(HDP_ADDR_CONFIG, gb_addr_config);
3258 WREG32(DMA_TILING_CONFIG + DMA0_REGISTER_OFFSET, gb_addr_config);
3259 WREG32(DMA_TILING_CONFIG + DMA1_REGISTER_OFFSET, gb_addr_config);
3261 WREG32(UVD_UDEC_ADDR_CONFIG, gb_addr_config);
3262 WREG32(UVD_UDEC_DB_ADDR_CONFIG, gb_addr_config);
3263 WREG32(UVD_UDEC_DBW_ADDR_CONFIG, gb_addr_config);