drm/radeon/rv730_dpm.c

227 				  RV770_SMC_STATETABLE *table)
239 	table->ACPIState = table->initialState;
240 	table->ACPIState.flags &= ~PPSMC_SWSTATE_FLAG_DC;
244 					  &table->ACPIState.levels[0].vddc);
245 		table->ACPIState.levels[0].gen2PCIE = pi->pcie_gen2 ?
247 		table->ACPIState.levels[0].gen2XSP =
251 					  &table->ACPIState.levels[0].vddc);
252 		table->ACPIState.levels[0].gen2PCIE = 0;
294 	table->ACPIState.levels[0].mclk.mclk730.vMPLL_FUNC_CNTL = cpu_to_be32(mpll_func_cntl);
295 	table->ACPIState.levels[0].mclk.mclk730.vMPLL_FUNC_CNTL2 = cpu_to_be32(mpll_func_cntl_2);
296 	table->ACPIState.levels[0].mclk.mclk730.vMPLL_FUNC_CNTL3 = cpu_to_be32(mpll_func_cntl_3);
297 	table->ACPIState.levels[0].mclk.mclk730.vMCLK_PWRMGT_CNTL = cpu_to_be32(mclk_pwrmgt_cntl);
298 	table->ACPIState.levels[0].mclk.mclk730.vDLL_CNTL = cpu_to_be32(dll_cntl);
300 	table->ACPIState.levels[0].mclk.mclk730.mclk_value = 0;
302 	table->ACPIState.levels[0].sclk.vCG_SPLL_FUNC_CNTL = cpu_to_be32(spll_func_cntl);
303 	table->ACPIState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_2 = cpu_to_be32(spll_func_cntl_2);
304 	table->ACPIState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_3 = cpu_to_be32(spll_func_cntl_3);
306 	table->ACPIState.levels[0].sclk.sclk_value = 0;
308 	rv770_populate_mvdd_value(rdev, 0, &table->ACPIState.levels[0].mvdd);
310 	table->ACPIState.levels[1] = table->ACPIState.levels[0];
311 	table->ACPIState.levels[2] = table->ACPIState.levels[0];
318 				     RV770_SMC_STATETABLE *table)
324 	table->initialState.levels[0].mclk.mclk730.vMPLL_FUNC_CNTL =
326 	table->initialState.levels[0].mclk.mclk730.vMPLL_FUNC_CNTL2 =
328 	table->initialState.levels[0].mclk.mclk730.vMPLL_FUNC_CNTL3 =
330 	table->initialState.levels[0].mclk.mclk730.vMCLK_PWRMGT_CNTL =
332 	table->initialState.levels[0].mclk.mclk730.vDLL_CNTL =
334 	table->initialState.levels[0].mclk.mclk730.vMPLL_SS =
336 	table->initialState.levels[0].mclk.mclk730.vMPLL_SS2 =
339 	table->initialState.levels[0].mclk.mclk730.mclk_value =
342 	table->initialState.levels[0].sclk.vCG_SPLL_FUNC_CNTL =
344 	table->initialState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_2 =
346 	table->initialState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_3 =
348 	table->initialState.levels[0].sclk.vCG_SPLL_SPREAD_SPECTRUM =
350 	table->initialState.levels[0].sclk.vCG_SPLL_SPREAD_SPECTRUM_2 =
353 	table->initialState.levels[0].sclk.sclk_value =
356 	table->initialState.levels[0].arbValue = MC_CG_ARB_FREQ_F0;
358 	table->initialState.levels[0].seqValue =
363 				  &table->initialState.levels[0].vddc);
365 					  &table->initialState.levels[0].mvdd);
369 	table->initialState.levels[0].aT = cpu_to_be32(a_t);
371 	table->initialState.levels[0].bSP = cpu_to_be32(pi->dsp);
374 		table->initialState.levels[0].gen2PCIE = 1;
376 		table->initialState.levels[0].gen2PCIE = 0;
378 		table->initialState.levels[0].gen2XSP = 1;
380 		table->initialState.levels[0].gen2XSP = 0;
382 	table->initialState.levels[1] = table->initialState.levels[0];
383 	table->initialState.levels[2] = table->initialState.levels[0];
385 	table->initialState.flags |= PPSMC_SWSTATE_FLAG_DC;