drm/radeon/rv6xx_dpm.c

240 				 u32 low, u32 high,
248 	rv6xx_convert_clock_to_stepping(rdev, low, &cur);
439 		state->low.sclk;
462 		state->low.mclk;
473 	if (state->medium.mclk == state->low.mclk)
488 	pi->hw.vddc[R600_POWER_LEVEL_LOW] = state->low.vddc;
497 		(state->low.flags & ATOM_PPLIB_R600_FLAGS_BACKBIASENABLE) ? true : false;
504 		(state->low.flags & ATOM_PPLIB_R600_FLAGS_PCIEGEN2) ? true : false;
516 	if ((state->medium.vddc == state->low.vddc) &&
518 	     (state->low.flags & ATOM_PPLIB_R600_FLAGS_BACKBIASENABLE)))
973 					new_state->low.vddc,
1027 	rv6xx_calculate_t(state->low.sclk,
1206 	safe_voltage = (new_state->low.vddc >= old_state->low.vddc) ?
1207 		new_state->low.vddc : old_state->low.vddc;
1222 					     old_state->low.vddc);
1235 	if ((new_state->low.flags & ATOM_PPLIB_R600_FLAGS_BACKBIASENABLE) &&
1236 	    (old_state->low.flags & ATOM_PPLIB_R600_FLAGS_BACKBIASENABLE))
1249 	if ((new_state->low.flags & ATOM_PPLIB_R600_FLAGS_PCIEGEN2) !=
1250 	    (old_state->low.flags & ATOM_PPLIB_R600_FLAGS_PCIEGEN2))
1311 	if (new_state->low.vddc > old_state->low.vddc)
1313 					     old_state->low.vddc,
1314 					     new_state->low.vddc);
1326 	if (new_state->low.vddc < old_state->low.vddc)
1328 					     old_state->low.vddc,
1329 					     new_state->low.vddc);
1426 			     old_state->low.sclk,
1427 			     new_state->low.sclk,
1439 				   new_state->low.sclk,
1460 			     new_state->low.sclk,
1504 		if (!(new_state->low.flags & ATOM_PPLIB_R600_FLAGS_PCIEGEN2))
1827 		pl = &ps->low;
2016 	pl = &ps->low;
2042 			pl = &ps->low;
2067 			pl = &ps->low;
2090 			pl = &ps->low;
2110 u32 rv6xx_dpm_get_sclk(struct radeon_device *rdev, bool low)
2114 	if (low)
2115 		return requested_state->low.sclk;
2120 u32 rv6xx_dpm_get_mclk(struct radeon_device *rdev, bool low)
2124 	if (low)
2125 		return requested_state->low.mclk;