Lines Matching defs:rdev
37 int rs690_mc_wait_for_idle(struct radeon_device *rdev)
42 for (i = 0; i < rdev->usec_timeout; i++) {
52 static void rs690_gpu_init(struct radeon_device *rdev)
55 r420_pipes_init(rdev);
56 if (rs690_mc_wait_for_idle(rdev)) {
66 void rs690_pm_info(struct radeon_device *rdev)
74 if (atom_parse_data_header(rdev->mode_info.atom_context, index, NULL,
76 info = (union igp_info *)(rdev->mode_info.atom_context->bios + data_offset);
82 rdev->pm.igp_sideport_mclk.full = dfixed_const(le32_to_cpu(info->info.ulBootUpMemoryClock));
83 rdev->pm.igp_sideport_mclk.full = dfixed_div(rdev->pm.igp_sideport_mclk, tmp);
85 rdev->pm.igp_system_mclk.full = dfixed_const(le16_to_cpu(info->info.usK8MemoryClock));
86 else if (rdev->clock.default_mclk) {
87 rdev->pm.igp_system_mclk.full = dfixed_const(rdev->clock.default_mclk);
88 rdev->pm.igp_system_mclk.full = dfixed_div(rdev->pm.igp_system_mclk, tmp);
90 rdev->pm.igp_system_mclk.full = dfixed_const(400);
91 rdev->pm.igp_ht_link_clk.full = dfixed_const(le16_to_cpu(info->info.usFSBClock));
92 rdev->pm.igp_ht_link_width.full = dfixed_const(info->info.ucHTLinkWidth);
96 rdev->pm.igp_sideport_mclk.full = dfixed_const(le32_to_cpu(info->info_v2.ulBootUpSidePortClock));
97 rdev->pm.igp_sideport_mclk.full = dfixed_div(rdev->pm.igp_sideport_mclk, tmp);
99 rdev->pm.igp_system_mclk.full = dfixed_const(le32_to_cpu(info->info_v2.ulBootUpUMAClock));
100 else if (rdev->clock.default_mclk)
101 rdev->pm.igp_system_mclk.full = dfixed_const(rdev->clock.default_mclk);
103 rdev->pm.igp_system_mclk.full = dfixed_const(66700);
104 rdev->pm.igp_system_mclk.full = dfixed_div(rdev->pm.igp_system_mclk, tmp);
105 rdev->pm.igp_ht_link_clk.full = dfixed_const(le32_to_cpu(info->info_v2.ulHTLinkFreq));
106 rdev->pm.igp_ht_link_clk.full = dfixed_div(rdev->pm.igp_ht_link_clk, tmp);
107 rdev->pm.igp_ht_link_width.full = dfixed_const(le16_to_cpu(info->info_v2.usMinHTLinkWidth));
111 rdev->pm.igp_sideport_mclk.full = dfixed_const(200);
112 rdev->pm.igp_system_mclk.full = dfixed_const(200);
113 rdev->pm.igp_ht_link_clk.full = dfixed_const(1000);
114 rdev->pm.igp_ht_link_width.full = dfixed_const(8);
120 rdev->pm.igp_sideport_mclk.full = dfixed_const(200);
121 rdev->pm.igp_system_mclk.full = dfixed_const(200);
122 rdev->pm.igp_ht_link_clk.full = dfixed_const(1000);
123 rdev->pm.igp_ht_link_width.full = dfixed_const(8);
129 rdev->pm.k8_bandwidth.full = dfixed_mul(rdev->pm.igp_system_mclk, tmp);
134 rdev->pm.ht_bandwidth.full = dfixed_mul(rdev->pm.igp_ht_link_clk,
135 rdev->pm.igp_ht_link_width);
136 rdev->pm.ht_bandwidth.full = dfixed_div(rdev->pm.ht_bandwidth, tmp);
137 if (tmp.full < rdev->pm.max_bandwidth.full) {
139 rdev->pm.max_bandwidth.full = tmp.full;
145 rdev->pm.sideport_bandwidth.full = dfixed_mul(rdev->pm.igp_sideport_mclk, tmp);
147 rdev->pm.sideport_bandwidth.full = dfixed_div(rdev->pm.sideport_bandwidth, tmp);
150 static void rs690_mc_init(struct radeon_device *rdev)
156 rs400_gart_adjust_size(rdev);
157 rdev->mc.vram_is_ddr = true;
158 rdev->mc.vram_width = 128;
159 rdev->mc.real_vram_size = RREG32(RADEON_CONFIG_MEMSIZE);
160 rdev->mc.mc_vram_size = rdev->mc.real_vram_size;
161 rdev->mc.aper_base = pci_resource_start(rdev->pdev, 0);
162 rdev->mc.aper_size = pci_resource_len(rdev->pdev, 0);
163 rdev->mc.visible_vram_size = rdev->mc.aper_size;
166 rdev->mc.igp_sideport_enabled = radeon_atombios_sideport_present(rdev);
171 if (rdev->mc.igp_sideport_enabled &&
172 (rdev->mc.real_vram_size == (384 * 1024 * 1024))) {
174 rdev->mc.real_vram_size -= 128 * 1024 * 1024;
175 rdev->mc.mc_vram_size = rdev->mc.real_vram_size;
179 rdev->fastfb_working = false;
184 if (k8_addr + rdev->mc.visible_vram_size < 0x100000000ULL)
190 if (!rdev->mc.igp_sideport_enabled && radeon_fastfb == 1) {
192 (unsigned long long)rdev->mc.aper_base, k8_addr);
193 rdev->mc.aper_base = (resource_size_t)k8_addr;
194 rdev->fastfb_working = true;
198 rs690_pm_info(rdev);
199 radeon_vram_location(rdev, &rdev->mc, base);
200 rdev->mc.gtt_base_align = rdev->mc.gtt_size - 1;
201 radeon_gtt_location(rdev, &rdev->mc);
202 radeon_update_bandwidth_info(rdev);
205 void rs690_line_buffer_adjust(struct radeon_device *rdev,
253 rdev->mode_info.crtcs[0]->lb_vblank_lead_lines = DIV_ROUND_UP(lb_size, mode1->crtc_hdisplay);
256 rdev->mode_info.crtcs[1]->lb_vblank_lead_lines = DIV_ROUND_UP(lb_size, mode2->crtc_hdisplay);
272 static void rs690_crtc_bandwidth_compute(struct radeon_device *rdev,
290 if (((rdev->family == CHIP_RS780) || (rdev->family == CHIP_RS880)) &&
291 (rdev->pm.pm_method == PM_METHOD_DPM) && rdev->pm.dpm_enabled)
292 selected_sclk = radeon_dpm_get_sclk(rdev, low);
294 selected_sclk = rdev->pm.current_sclk;
303 core_bandwidth.full = dfixed_div(rdev->pm.sclk, a);
366 if (rdev->mc.igp_sideport_enabled) {
367 if (max_bandwidth.full > rdev->pm.sideport_bandwidth.full &&
368 rdev->pm.sideport_bandwidth.full)
369 max_bandwidth = rdev->pm.sideport_bandwidth;
372 b.full = dfixed_div(rdev->pm.igp_sideport_mclk, a);
376 if (max_bandwidth.full > rdev->pm.k8_bandwidth.full &&
377 rdev->pm.k8_bandwidth.full)
378 max_bandwidth = rdev->pm.k8_bandwidth;
379 if (max_bandwidth.full > rdev->pm.ht_bandwidth.full &&
380 rdev->pm.ht_bandwidth.full)
381 max_bandwidth = rdev->pm.ht_bandwidth;
460 static void rs690_compute_mode_priority(struct radeon_device *rdev,
523 if (rdev->disp_priority == 2) {
552 if (rdev->disp_priority == 2)
579 if (rdev->disp_priority == 2)
584 void rs690_bandwidth_update(struct radeon_device *rdev)
594 if (!rdev->mode_info.mode_config_initialized)
597 radeon_update_display_priority(rdev);
599 if (rdev->mode_info.crtcs[0]->base.enabled)
600 mode0 = &rdev->mode_info.crtcs[0]->base.mode;
601 if (rdev->mode_info.crtcs[1]->base.enabled)
602 mode1 = &rdev->mode_info.crtcs[1]->base.mode;
608 if ((rdev->disp_priority == 2) &&
609 ((rdev->family == CHIP_RS690) || (rdev->family == CHIP_RS740))) {
619 rs690_line_buffer_adjust(rdev, mode0, mode1);
621 if ((rdev->family == CHIP_RS690) || (rdev->family == CHIP_RS740))
623 if ((rdev->family == CHIP_RS780) || (rdev->family == CHIP_RS880))
626 rs690_crtc_bandwidth_compute(rdev, rdev->mode_info.crtcs[0], &wm0_high, false);
627 rs690_crtc_bandwidth_compute(rdev, rdev->mode_info.crtcs[1], &wm1_high, false);
629 rs690_crtc_bandwidth_compute(rdev, rdev->mode_info.crtcs[0], &wm0_low, true);
630 rs690_crtc_bandwidth_compute(rdev, rdev->mode_info.crtcs[1], &wm1_low, true);
636 rs690_compute_mode_priority(rdev,
640 rs690_compute_mode_priority(rdev,
651 uint32_t rs690_mc_rreg(struct radeon_device *rdev, uint32_t reg)
656 spin_lock_irqsave(&rdev->mc_idx_lock, flags);
660 spin_unlock_irqrestore(&rdev->mc_idx_lock, flags);
664 void rs690_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
668 spin_lock_irqsave(&rdev->mc_idx_lock, flags);
673 spin_unlock_irqrestore(&rdev->mc_idx_lock, flags);
676 static void rs690_mc_program(struct radeon_device *rdev)
681 rv515_mc_stop(rdev, &save);
684 if (rs690_mc_wait_for_idle(rdev))
685 dev_warn(rdev->dev, "Wait MC idle timeout before updating MC.\n");
688 S_000100_MC_FB_START(rdev->mc.vram_start >> 16) |
689 S_000100_MC_FB_TOP(rdev->mc.vram_end >> 16));
691 S_000134_HDP_FB_START(rdev->mc.vram_start >> 16));
693 rv515_mc_resume(rdev, &save);
696 static int rs690_startup(struct radeon_device *rdev)
700 rs690_mc_program(rdev);
702 rv515_clock_startup(rdev);
704 rs690_gpu_init(rdev);
707 r = rs400_gart_enable(rdev);
712 r = radeon_wb_init(rdev);
716 r = radeon_fence_driver_start_ring(rdev, RADEON_RING_TYPE_GFX_INDEX);
718 dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r);
723 if (!rdev->irq.installed) {
724 r = radeon_irq_kms_init(rdev);
729 rs600_irq_set(rdev);
730 rdev->config.r300.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL);
732 r = r100_cp_init(rdev, 1024 * 1024);
734 dev_err(rdev->dev, "failed initializing CP (%d).\n", r);
738 r = radeon_ib_pool_init(rdev);
740 dev_err(rdev->dev, "IB initialization failed (%d).\n", r);
744 r = radeon_audio_init(rdev);
746 dev_err(rdev->dev, "failed initializing audio\n");
753 int rs690_resume(struct radeon_device *rdev)
758 rs400_gart_disable(rdev);
760 rv515_clock_startup(rdev);
762 if (radeon_asic_reset(rdev)) {
763 dev_warn(rdev->dev, "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
768 atom_asic_init(rdev->mode_info.atom_context);
770 rv515_clock_startup(rdev);
772 radeon_surface_init(rdev);
774 rdev->accel_working = true;
775 r = rs690_startup(rdev);
777 rdev->accel_working = false;
782 int rs690_suspend(struct radeon_device *rdev)
784 radeon_pm_suspend(rdev);
785 radeon_audio_fini(rdev);
786 r100_cp_disable(rdev);
787 radeon_wb_disable(rdev);
788 rs600_irq_disable(rdev);
789 rs400_gart_disable(rdev);
793 void rs690_fini(struct radeon_device *rdev)
795 radeon_pm_fini(rdev);
796 radeon_audio_fini(rdev);
797 r100_cp_fini(rdev);
798 radeon_wb_fini(rdev);
799 radeon_ib_pool_fini(rdev);
800 radeon_gem_fini(rdev);
801 rs400_gart_fini(rdev);
802 radeon_irq_kms_fini(rdev);
803 radeon_fence_driver_fini(rdev);
804 radeon_bo_fini(rdev);
805 radeon_atombios_fini(rdev);
806 kfree(rdev->bios);
807 rdev->bios = NULL;
810 int rs690_init(struct radeon_device *rdev)
815 rv515_vga_render_disable(rdev);
817 radeon_scratch_init(rdev);
819 radeon_surface_init(rdev);
821 r100_restore_sanity(rdev);
824 if (!radeon_get_bios(rdev)) {
825 if (ASIC_IS_AVIVO(rdev))
828 if (rdev->is_atom_bios) {
829 r = radeon_atombios_init(rdev);
833 dev_err(rdev->dev, "Expecting atombios for RV515 GPU\n");
837 if (radeon_asic_reset(rdev)) {
838 dev_warn(rdev->dev,
844 if (radeon_boot_test_post_card(rdev) == false)
848 radeon_get_clock_info(rdev->ddev);
850 rs690_mc_init(rdev);
851 rv515_debugfs(rdev);
853 radeon_fence_driver_init(rdev);
855 r = radeon_bo_init(rdev);
858 r = rs400_gart_init(rdev);
861 rs600_set_safe_registers(rdev);
864 radeon_pm_init(rdev);
866 rdev->accel_working = true;
867 r = rs690_startup(rdev);
870 dev_err(rdev->dev, "Disabling GPU acceleration\n");
871 r100_cp_fini(rdev);
872 radeon_wb_fini(rdev);
873 radeon_ib_pool_fini(rdev);
874 rs400_gart_fini(rdev);
875 radeon_irq_kms_fini(rdev);
876 rdev->accel_working = false;