drm/radeon/radeon_gem.c

300 	struct drm_radeon_gem_info *args = data;
305 	args->vram_size = (u64)man->size << PAGE_SHIFT;
306 	args->vram_visible = rdev->mc.visible_vram_size;
307 	args->vram_visible -= rdev->vram_pin_size;
308 	args->gart_size = rdev->mc.gtt_size;
309 	args->gart_size -= rdev->gart_pin_size;
318 	struct drm_radeon_gem_create *args = data;
325 	args->size = roundup(args->size, PAGE_SIZE);
326 	r = radeon_gem_object_create(rdev, args->size, args->alignment,
327 				     args->initial_domain, args->flags,
342 	args->handle = handle;
352 	struct drm_radeon_gem_userptr *args = data;
358 	args->addr = untagged_addr(args->addr);
360 	if (offset_in_page(args->addr | args->size))
364 	if (args->flags & ~(RADEON_GEM_USERPTR_READONLY |
369 	if (args->flags & RADEON_GEM_USERPTR_READONLY) {
374 	} else if (!(args->flags & RADEON_GEM_USERPTR_ANONONLY) ||
375 		   !(args->flags & RADEON_GEM_USERPTR_REGISTER)) {
385 	r = radeon_gem_object_create(rdev, args->size, 0,
392 	r = radeon_ttm_tt_set_userptr(rdev, bo->tbo.ttm, args->addr, args->flags);
396 	if (args->flags & RADEON_GEM_USERPTR_REGISTER) {
397 		r = radeon_mn_register(bo, args->addr);
402 	if (args->flags & RADEON_GEM_USERPTR_VALIDATE) {
424 	args->handle = handle;
444 	struct drm_radeon_gem_set_domain *args = data;
453 	gobj = drm_gem_object_lookup(filp, args->handle);
459 	r = radeon_gem_set_domain(gobj, args->read_domains, args->write_domain);
491 	struct drm_radeon_gem_mmap *args = data;
493 	return radeon_mode_dumb_mmap(filp, dev, args->handle, &args->addr_ptr);
499 	struct drm_radeon_gem_busy *args = data;
505 	gobj = drm_gem_object_lookup(filp, args->handle);
518 	args->domain = radeon_mem_type_to_domain(cur_placement);
527 	struct drm_radeon_gem_wait_idle *args = data;
534 	gobj = drm_gem_object_lookup(filp, args->handle);
560 	struct drm_radeon_gem_set_tiling *args = data;
565 	DRM_DEBUG("%d \n", args->handle);
566 	gobj = drm_gem_object_lookup(filp, args->handle);
570 	r = radeon_bo_set_tiling_flags(robj, args->tiling_flags, args->pitch);
578 	struct drm_radeon_gem_get_tiling *args = data;
584 	gobj = drm_gem_object_lookup(filp, args->handle);
591 	radeon_bo_get_tiling_flags(rbo, &args->tiling_flags, &args->pitch);
663 	struct drm_radeon_gem_va *args = data;
673 		args->operation = RADEON_VA_RESULT_ERROR;
682 	if (args->vm_id) {
683 		args->operation = RADEON_VA_RESULT_ERROR;
687 	if (args->offset < RADEON_VA_RESERVED_SIZE) {
690 			(unsigned long)args->offset,
692 		args->operation = RADEON_VA_RESULT_ERROR;
701 	if ((args->flags & invalid_flags)) {
703 			args->flags, invalid_flags);
704 		args->operation = RADEON_VA_RESULT_ERROR;
708 	switch (args->operation) {
714 			args->operation);
715 		args->operation = RADEON_VA_RESULT_ERROR;
719 	gobj = drm_gem_object_lookup(filp, args->handle);
721 		args->operation = RADEON_VA_RESULT_ERROR;
727 		args->operation = RADEON_VA_RESULT_ERROR;
733 		args->operation = RADEON_VA_RESULT_ERROR;
739 	switch (args->operation) {
742 			args->operation = RADEON_VA_RESULT_VA_EXIST;
743 			args->offset = bo_va->it.start * RADEON_GPU_PAGE_SIZE;
747 		r = radeon_vm_bo_set_addr(rdev, bo_va, args->offset, args->flags);
757 	args->operation = RADEON_VA_RESULT_OK;
759 		args->operation = RADEON_VA_RESULT_ERROR;
769 	struct drm_radeon_gem_op *args = data;
774 	gobj = drm_gem_object_lookup(filp, args->handle);
788 	switch (args->op) {
790 		args->value = robj->initial_domain;
793 		robj->initial_domain = args->value & (RADEON_GEM_DOMAIN_VRAM |
833 			    struct drm_mode_create_dumb *args)
840 	args->pitch = radeon_align_pitch(rdev, args->width,
841 					 DIV_ROUND_UP(args->bpp, 8), 0);
842 	args->size = (u64)args->pitch * args->height;
843 	args->size = ALIGN(args->size, PAGE_SIZE);
845 	r = radeon_gem_object_create(rdev, args->size, 0,
857 	args->handle = handle;