drm/radeon/radeon_fence.c

68 	struct radeon_fence_driver *drv = &rdev->fence_drv[ring];
89 	struct radeon_fence_driver *drv = &rdev->fence_drv[ring];
118 			   &rdev->fence_drv[ring].lockup_work,
144 	(*fence)->seq = seq = ++rdev->fence_drv[ring].sync_seq[ring];
176 	seq = atomic64_read(&fence->rdev->fence_drv[fence->ring].last_seq);
223 	last_seq = atomic64_read(&rdev->fence_drv[ring].last_seq);
225 		last_emitted = rdev->fence_drv[ring].sync_seq[ring];
250 	} while (atomic64_xchg(&rdev->fence_drv[ring].last_seq, seq) > seq);
268 	struct radeon_fence_driver *fence_drv;
272 	fence_drv = container_of(work, struct radeon_fence_driver,
274 	rdev = fence_drv->rdev;
275 	ring = fence_drv - &rdev->fence_drv[0];
283 	if (fence_drv->delayed_irq && rdev->irq.installed) {
286 		fence_drv->delayed_irq = false;
299 			 (uint64_t)atomic64_read(&fence_drv->last_seq),
300 			 fence_drv->sync_seq[ring], ring);
341 	if (atomic64_read(&rdev->fence_drv[ring].last_seq) >= seq)
346 	if (atomic64_read(&rdev->fence_drv[ring].last_seq) >= seq)
359 	if (atomic64_read(&rdev->fence_drv[ring].last_seq) >= seq)
366 		if (atomic64_read(&rdev->fence_drv[ring].last_seq) >= seq)
385 	if (atomic64_read(&rdev->fence_drv[fence->ring].last_seq) >= fence->seq)
395 		if (atomic64_read(&rdev->fence_drv[fence->ring].last_seq) >= fence->seq) {
405 			rdev->fence_drv[fence->ring].delayed_irq = true;
633 	seq[ring] = atomic64_read(&rdev->fence_drv[ring].last_seq) + 1ULL;
634 	if (seq[ring] >= rdev->fence_drv[ring].sync_seq[ring]) {
663 	seq[ring] = rdev->fence_drv[ring].sync_seq[ring];
726 	emitted = rdev->fence_drv[ring].sync_seq[ring]
727 		- atomic64_read(&rdev->fence_drv[ring].last_seq);
757 	fdrv = &fence->rdev->fence_drv[dst_ring];
785 	src = &fence->rdev->fence_drv[fence->ring];
786 	dst = &fence->rdev->fence_drv[dst_ring];
812 	radeon_scratch_free(rdev, rdev->fence_drv[ring].scratch_reg);
814 		rdev->fence_drv[ring].scratch_reg = 0;
817 			rdev->fence_drv[ring].cpu_addr = &rdev->wb.wb[index/4];
818 			rdev->fence_drv[ring].gpu_addr = rdev->wb.gpu_addr +
824 			rdev->fence_drv[ring].cpu_addr = rdev->uvd.cpu_addr + index;
825 			rdev->fence_drv[ring].gpu_addr = rdev->uvd.gpu_addr + index;
829 		r = radeon_scratch_get(rdev, &rdev->fence_drv[ring].scratch_reg);
835 			rdev->fence_drv[ring].scratch_reg -
837 		rdev->fence_drv[ring].cpu_addr = &rdev->wb.wb[index/4];
838 		rdev->fence_drv[ring].gpu_addr = rdev->wb.gpu_addr + index;
840 	radeon_fence_write(rdev, atomic64_read(&rdev->fence_drv[ring].last_seq), ring);
841 	rdev->fence_drv[ring].initialized = true;
843 		 ring, rdev->fence_drv[ring].gpu_addr);
861 	rdev->fence_drv[ring].scratch_reg = -1;
862 	rdev->fence_drv[ring].cpu_addr = NULL;
863 	rdev->fence_drv[ring].gpu_addr = 0;
865 		rdev->fence_drv[ring].sync_seq[i] = 0;
866 	atomic64_set(&rdev->fence_drv[ring].last_seq, 0);
867 	rdev->fence_drv[ring].initialized = false;
868 	INIT_DELAYED_WORK(&rdev->fence_drv[ring].lockup_work,
870 	rdev->fence_drv[ring].rdev = rdev;
909 		if (!rdev->fence_drv[ring].initialized)
916 		cancel_delayed_work_sync(&rdev->fence_drv[ring].lockup_work);
918 		radeon_scratch_free(rdev, rdev->fence_drv[ring].scratch_reg);
919 		rdev->fence_drv[ring].initialized = false;
935 	if (rdev->fence_drv[ring].initialized) {
936 		radeon_fence_write(rdev, rdev->fence_drv[ring].sync_seq[ring], ring);
937 		cancel_delayed_work_sync(&rdev->fence_drv[ring].lockup_work);
952 		if (!rdev->fence_drv[i].initialized)
959 			   (unsigned long long)atomic64_read(&rdev->fence_drv[i].last_seq));
961 			   rdev->fence_drv[i].sync_seq[i]);
964 			if (i != j && rdev->fence_drv[j].initialized)
966 					   j, rdev->fence_drv[i].sync_seq[j]);