Lines Matching defs:tmp
200 u32 tmp = RREG32_PLL(RADEON_PPLL_REF_DIV);
203 (tmp & R300_PPLL_REF_DIV_ACC_MASK) >> R300_PPLL_REF_DIV_ACC_SHIFT;
205 p1pll->reference_div = tmp & RADEON_PPLL_REF_DIV_MASK;
393 uint32_t tmp;
400 tmp = RREG32_PLL(RADEON_CLK_PIN_CNTL);
401 tmp &= ~RADEON_DONT_USE_XTALIN;
402 WREG32_PLL(RADEON_CLK_PIN_CNTL, tmp);
404 tmp = RREG32_PLL(RADEON_SCLK_CNTL);
405 tmp &= ~RADEON_SCLK_SRC_SEL_MASK;
406 WREG32_PLL(RADEON_SCLK_CNTL, tmp);
410 tmp = RREG32_PLL(RADEON_SPLL_CNTL);
411 tmp |= RADEON_SPLL_SLEEP;
412 WREG32_PLL(RADEON_SPLL_CNTL, tmp);
416 tmp = RREG32_PLL(RADEON_SPLL_CNTL);
417 tmp |= RADEON_SPLL_RESET;
418 WREG32_PLL(RADEON_SPLL_CNTL, tmp);
422 tmp = RREG32_PLL(RADEON_M_SPLL_REF_FB_DIV);
423 tmp &= ~(RADEON_SPLL_FB_DIV_MASK << RADEON_SPLL_FB_DIV_SHIFT);
424 tmp |= (fb_div & RADEON_SPLL_FB_DIV_MASK) << RADEON_SPLL_FB_DIV_SHIFT;
425 WREG32_PLL(RADEON_M_SPLL_REF_FB_DIV, tmp);
428 tmp = RREG32_PLL(RADEON_SPLL_CNTL);
429 tmp &= ~RADEON_SPLL_PVG_MASK;
431 tmp |= (0x7 << RADEON_SPLL_PVG_SHIFT);
433 tmp |= (0x4 << RADEON_SPLL_PVG_SHIFT);
434 WREG32_PLL(RADEON_SPLL_CNTL, tmp);
436 tmp = RREG32_PLL(RADEON_SPLL_CNTL);
437 tmp &= ~RADEON_SPLL_SLEEP;
438 WREG32_PLL(RADEON_SPLL_CNTL, tmp);
442 tmp = RREG32_PLL(RADEON_SPLL_CNTL);
443 tmp &= ~RADEON_SPLL_RESET;
444 WREG32_PLL(RADEON_SPLL_CNTL, tmp);
448 tmp = RREG32_PLL(RADEON_SCLK_CNTL);
449 tmp &= ~RADEON_SCLK_SRC_SEL_MASK;
453 tmp |= 1;
456 tmp |= 2;
459 tmp |= 3;
462 tmp |= 4;
465 WREG32_PLL(RADEON_SCLK_CNTL, tmp);
469 tmp = RREG32_PLL(RADEON_CLK_PIN_CNTL);
470 tmp |= RADEON_DONT_USE_XTALIN;
471 WREG32_PLL(RADEON_CLK_PIN_CNTL, tmp);
478 uint32_t tmp;
482 tmp = RREG32_PLL(RADEON_SCLK_CNTL);
486 tmp &=
490 tmp &=
496 WREG32_PLL(RADEON_SCLK_CNTL, tmp);
500 tmp = RREG32_PLL(RADEON_SCLK_CNTL);
501 tmp &=
515 tmp |= RADEON_DYN_STOP_LAT_MASK;
516 tmp |=
519 WREG32_PLL(RADEON_SCLK_CNTL, tmp);
521 tmp = RREG32_PLL(RADEON_SCLK_MORE_CNTL);
522 tmp &= ~RADEON_SCLK_MORE_FORCEON;
523 tmp |= RADEON_SCLK_MORE_MAX_DYN_STOP_LAT;
524 WREG32_PLL(RADEON_SCLK_MORE_CNTL, tmp);
526 tmp = RREG32_PLL(RADEON_VCLK_ECP_CNTL);
527 tmp |= (RADEON_PIXCLK_ALWAYS_ONb |
529 WREG32_PLL(RADEON_VCLK_ECP_CNTL, tmp);
531 tmp = RREG32_PLL(RADEON_PIXCLKS_CNTL);
532 tmp |= (RADEON_PIX2CLK_ALWAYS_ONb |
545 WREG32_PLL(RADEON_PIXCLKS_CNTL, tmp);
547 tmp = RREG32_PLL(R300_SCLK_CNTL2);
548 tmp &= ~(R300_SCLK_FORCE_TCL |
551 tmp |= (R300_SCLK_TCL_MAX_DYN_STOP_LAT |
554 WREG32_PLL(R300_SCLK_CNTL2, tmp);
556 tmp = RREG32_PLL(RADEON_SCLK_CNTL);
557 tmp &=
571 tmp |= RADEON_DYN_STOP_LAT_MASK;
572 WREG32_PLL(RADEON_SCLK_CNTL, tmp);
574 tmp = RREG32_PLL(RADEON_SCLK_MORE_CNTL);
575 tmp &= ~RADEON_SCLK_MORE_FORCEON;
576 tmp |= RADEON_SCLK_MORE_MAX_DYN_STOP_LAT;
577 WREG32_PLL(RADEON_SCLK_MORE_CNTL, tmp);
579 tmp = RREG32_PLL(RADEON_VCLK_ECP_CNTL);
580 tmp |= (RADEON_PIXCLK_ALWAYS_ONb |
582 WREG32_PLL(RADEON_VCLK_ECP_CNTL, tmp);
584 tmp = RREG32_PLL(RADEON_PIXCLKS_CNTL);
585 tmp |= (RADEON_PIX2CLK_ALWAYS_ONb |
598 WREG32_PLL(RADEON_PIXCLKS_CNTL, tmp);
600 tmp = RREG32_PLL(RADEON_MCLK_MISC);
601 tmp |= (RADEON_MC_MCLK_DYN_ENABLE |
603 WREG32_PLL(RADEON_MCLK_MISC, tmp);
605 tmp = RREG32_PLL(RADEON_MCLK_CNTL);
606 tmp |= (RADEON_FORCEON_MCLKA |
609 tmp &= ~(RADEON_FORCEON_YCLKA |
617 if ((tmp & R300_DISABLE_MC_MCLKA) &&
618 (tmp & R300_DISABLE_MC_MCLKB)) {
620 tmp = RREG32_PLL(RADEON_MCLK_CNTL);
624 tmp &=
627 tmp &=
630 tmp &= ~(R300_DISABLE_MC_MCLKA |
635 WREG32_PLL(RADEON_MCLK_CNTL, tmp);
637 tmp = RREG32_PLL(RADEON_SCLK_CNTL);
638 tmp &= ~(R300_SCLK_FORCE_VAP);
639 tmp |= RADEON_SCLK_FORCE_CP;
640 WREG32_PLL(RADEON_SCLK_CNTL, tmp);
643 tmp = RREG32_PLL(R300_SCLK_CNTL2);
644 tmp &= ~(R300_SCLK_FORCE_TCL |
647 WREG32_PLL(R300_SCLK_CNTL2, tmp);
650 tmp = RREG32_PLL(RADEON_CLK_PWRMGT_CNTL);
652 tmp &= ~(RADEON_ACTIVE_HILO_LAT_MASK |
656 tmp |= (RADEON_ENGIN_DYNCLK_MODE |
658 WREG32_PLL(RADEON_CLK_PWRMGT_CNTL, tmp);
661 tmp = RREG32_PLL(RADEON_CLK_PIN_CNTL);
662 tmp |= RADEON_SCLK_DYN_START_CNTL;
663 WREG32_PLL(RADEON_CLK_PIN_CNTL, tmp);
669 tmp = RREG32_PLL(RADEON_SCLK_CNTL);
670 /*tmp &= RADEON_SCLK_SRC_SEL_MASK; */
671 tmp &= ~RADEON_SCLK_FORCEON_MASK;
683 tmp |= RADEON_SCLK_FORCE_CP;
684 tmp |= RADEON_SCLK_FORCE_VIP;
687 WREG32_PLL(RADEON_SCLK_CNTL, tmp);
692 tmp = RREG32_PLL(RADEON_SCLK_MORE_CNTL);
693 tmp &= ~RADEON_SCLK_MORE_FORCEON;
701 tmp |= RADEON_SCLK_MORE_FORCEON;
703 WREG32_PLL(RADEON_SCLK_MORE_CNTL, tmp);
713 tmp = RREG32_PLL(RADEON_PLL_PWRMGT_CNTL);
714 tmp |= RADEON_TCL_BYPASS_DISABLE;
715 WREG32_PLL(RADEON_PLL_PWRMGT_CNTL, tmp);
720 tmp = RREG32_PLL(RADEON_PIXCLKS_CNTL);
721 tmp |= (RADEON_PIX2CLK_ALWAYS_ONb |
729 WREG32_PLL(RADEON_PIXCLKS_CNTL, tmp);
732 tmp = RREG32_PLL(RADEON_VCLK_ECP_CNTL);
733 tmp |= (RADEON_PIXCLK_ALWAYS_ONb |
736 WREG32_PLL(RADEON_VCLK_ECP_CNTL, tmp);
742 tmp = RREG32_PLL(RADEON_SCLK_CNTL);
743 tmp |= (RADEON_SCLK_FORCE_CP | RADEON_SCLK_FORCE_HDP |
750 WREG32_PLL(RADEON_SCLK_CNTL, tmp);
753 tmp = RREG32_PLL(RADEON_SCLK_CNTL);
754 tmp |= (RADEON_SCLK_FORCE_DISP2 | RADEON_SCLK_FORCE_CP |
762 WREG32_PLL(RADEON_SCLK_CNTL, tmp);
764 tmp = RREG32_PLL(RADEON_SCLK_MORE_CNTL);
765 tmp |= RADEON_SCLK_MORE_FORCEON;
766 WREG32_PLL(RADEON_SCLK_MORE_CNTL, tmp);
768 tmp = RREG32_PLL(RADEON_VCLK_ECP_CNTL);
769 tmp &= ~(RADEON_PIXCLK_ALWAYS_ONb |
772 WREG32_PLL(RADEON_VCLK_ECP_CNTL, tmp);
774 tmp = RREG32_PLL(RADEON_PIXCLKS_CNTL);
775 tmp &= ~(RADEON_PIX2CLK_ALWAYS_ONb |
789 WREG32_PLL(RADEON_PIXCLKS_CNTL, tmp);
792 tmp = RREG32_PLL(R300_SCLK_CNTL2);
793 tmp |= (R300_SCLK_FORCE_TCL |
795 WREG32_PLL(R300_SCLK_CNTL2, tmp);
797 tmp = RREG32_PLL(RADEON_SCLK_CNTL);
798 tmp |= (RADEON_SCLK_FORCE_DISP2 | RADEON_SCLK_FORCE_CP |
806 WREG32_PLL(RADEON_SCLK_CNTL, tmp);
808 tmp = RREG32_PLL(RADEON_SCLK_MORE_CNTL);
809 tmp |= RADEON_SCLK_MORE_FORCEON;
810 WREG32_PLL(RADEON_SCLK_MORE_CNTL, tmp);
812 tmp = RREG32_PLL(RADEON_MCLK_CNTL);
813 tmp |= (RADEON_FORCEON_MCLKA |
817 WREG32_PLL(RADEON_MCLK_CNTL, tmp);
819 tmp = RREG32_PLL(RADEON_VCLK_ECP_CNTL);
820 tmp &= ~(RADEON_PIXCLK_ALWAYS_ONb |
823 WREG32_PLL(RADEON_VCLK_ECP_CNTL, tmp);
825 tmp = RREG32_PLL(RADEON_PIXCLKS_CNTL);
826 tmp &= ~(RADEON_PIX2CLK_ALWAYS_ONb |
840 WREG32_PLL(RADEON_PIXCLKS_CNTL, tmp);
842 tmp = RREG32_PLL(RADEON_SCLK_CNTL);
843 tmp |= (RADEON_SCLK_FORCE_CP | RADEON_SCLK_FORCE_E2);
844 tmp |= RADEON_SCLK_FORCE_SE;
847 tmp |= (RADEON_SCLK_FORCE_RB |
860 tmp |= (RADEON_SCLK_FORCE_HDP |
867 WREG32_PLL(RADEON_SCLK_CNTL, tmp);
873 tmp = RREG32_PLL(R300_SCLK_CNTL2);
874 tmp |= (R300_SCLK_FORCE_TCL |
877 WREG32_PLL(R300_SCLK_CNTL2, tmp);
882 tmp = RREG32_PLL(RADEON_MCLK_CNTL);
883 tmp &= ~(RADEON_FORCEON_MCLKA |
885 WREG32_PLL(RADEON_MCLK_CNTL, tmp);
892 tmp = RREG32_PLL(RADEON_SCLK_MORE_CNTL);
893 tmp |= RADEON_SCLK_MORE_FORCEON;
894 WREG32_PLL(RADEON_SCLK_MORE_CNTL, tmp);
898 tmp = RREG32_PLL(RADEON_PIXCLKS_CNTL);
899 tmp &= ~(RADEON_PIX2CLK_ALWAYS_ONb |
907 WREG32_PLL(RADEON_PIXCLKS_CNTL, tmp);
910 tmp = RREG32_PLL(RADEON_VCLK_ECP_CNTL);
911 tmp &= ~(RADEON_PIXCLK_ALWAYS_ONb |
913 WREG32_PLL(RADEON_VCLK_ECP_CNTL, tmp);