Lines Matching refs:power_state
2047 rdev->pm.power_state[state_index].misc = misc;
2048 rdev->pm.power_state[state_index].misc2 = misc2;
2051 rdev->pm.power_state[state_index].type =
2054 rdev->pm.power_state[state_index].type =
2057 rdev->pm.power_state[state_index].type =
2060 rdev->pm.power_state[state_index].type =
2063 rdev->pm.power_state[state_index].type =
2065 rdev->pm.power_state[state_index].flags &=
2069 rdev->pm.power_state[state_index].type =
2072 rdev->pm.power_state[state_index].type =
2075 rdev->pm.power_state[state_index].default_clock_mode =
2076 &rdev->pm.power_state[state_index].clock_info[0];
2078 rdev->pm.power_state[state_index].clock_info[0].flags |=
2122 rdev->pm.power_state = kcalloc(num_modes,
2125 if (!rdev->pm.power_state)
2130 if (!rdev->pm.power_state[state_index].clock_info) {
2131 rdev->pm.power_state[state_index].clock_info =
2135 if (!rdev->pm.power_state[state_index].clock_info)
2137 rdev->pm.power_state[state_index].num_clock_modes = 1;
2138 rdev->pm.power_state[state_index].clock_info[0].voltage.type = VOLTAGE_NONE;
2141 rdev->pm.power_state[state_index].clock_info[0].mclk =
2143 rdev->pm.power_state[state_index].clock_info[0].sclk =
2146 if ((rdev->pm.power_state[state_index].clock_info[0].mclk == 0) ||
2147 (rdev->pm.power_state[state_index].clock_info[0].sclk == 0))
2149 rdev->pm.power_state[state_index].pcie_lanes =
2154 rdev->pm.power_state[state_index].clock_info[0].voltage.type =
2156 rdev->pm.power_state[state_index].clock_info[0].voltage.gpio =
2160 rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
2163 rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
2166 rdev->pm.power_state[state_index].clock_info[0].voltage.type =
2168 rdev->pm.power_state[state_index].clock_info[0].voltage.vddc_id =
2171 rdev->pm.power_state[state_index].flags = RADEON_PM_STATE_SINGLE_DISPLAY_ONLY;
2176 rdev->pm.power_state[state_index].clock_info[0].mclk =
2178 rdev->pm.power_state[state_index].clock_info[0].sclk =
2181 if ((rdev->pm.power_state[state_index].clock_info[0].mclk == 0) ||
2182 (rdev->pm.power_state[state_index].clock_info[0].sclk == 0))
2184 rdev->pm.power_state[state_index].pcie_lanes =
2190 rdev->pm.power_state[state_index].clock_info[0].voltage.type =
2192 rdev->pm.power_state[state_index].clock_info[0].voltage.gpio =
2196 rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
2199 rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
2202 rdev->pm.power_state[state_index].clock_info[0].voltage.type =
2204 rdev->pm.power_state[state_index].clock_info[0].voltage.vddc_id =
2207 rdev->pm.power_state[state_index].flags = RADEON_PM_STATE_SINGLE_DISPLAY_ONLY;
2212 rdev->pm.power_state[state_index].clock_info[0].mclk =
2214 rdev->pm.power_state[state_index].clock_info[0].sclk =
2217 if ((rdev->pm.power_state[state_index].clock_info[0].mclk == 0) ||
2218 (rdev->pm.power_state[state_index].clock_info[0].sclk == 0))
2220 rdev->pm.power_state[state_index].pcie_lanes =
2226 rdev->pm.power_state[state_index].clock_info[0].voltage.type =
2228 rdev->pm.power_state[state_index].clock_info[0].voltage.gpio =
2232 rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
2235 rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
2238 rdev->pm.power_state[state_index].clock_info[0].voltage.type =
2240 rdev->pm.power_state[state_index].clock_info[0].voltage.vddc_id =
2243 rdev->pm.power_state[state_index].clock_info[0].voltage.vddci_enabled =
2245 rdev->pm.power_state[state_index].clock_info[0].voltage.vddci_id =
2249 rdev->pm.power_state[state_index].flags = RADEON_PM_STATE_SINGLE_DISPLAY_ONLY;
2258 kfree(rdev->pm.power_state[state_index].clock_info);
2259 rdev->pm.power_state[state_index].clock_info = NULL;
2264 rdev->pm.power_state[state_index - 1].type =
2267 rdev->pm.power_state[state_index - 1].default_clock_mode =
2268 &rdev->pm.power_state[state_index - 1].clock_info[0];
2269 rdev->pm.power_state[state_index - 1].flags &=
2271 rdev->pm.power_state[state_index - 1].misc = 0;
2272 rdev->pm.power_state[state_index - 1].misc2 = 0;
2413 rdev->pm.power_state[state_index].misc = misc;
2414 rdev->pm.power_state[state_index].misc2 = misc2;
2415 rdev->pm.power_state[state_index].pcie_lanes =
2420 rdev->pm.power_state[state_index].type =
2424 rdev->pm.power_state[state_index].type =
2428 rdev->pm.power_state[state_index].type =
2433 rdev->pm.power_state[state_index].type =
2437 rdev->pm.power_state[state_index].flags = 0;
2439 rdev->pm.power_state[state_index].flags |=
2442 rdev->pm.power_state[state_index].type =
2445 rdev->pm.power_state[state_index].default_clock_mode =
2446 &rdev->pm.power_state[state_index].clock_info[mode_index - 1];
2449 rdev->pm.default_sclk = rdev->pm.power_state[state_index].clock_info[0].sclk;
2450 rdev->pm.default_mclk = rdev->pm.power_state[state_index].clock_info[0].mclk;
2451 rdev->pm.default_vddc = rdev->pm.power_state[state_index].clock_info[0].voltage.voltage;
2452 rdev->pm.default_vddci = rdev->pm.power_state[state_index].clock_info[0].voltage.vddci;
2462 rdev->pm.power_state[state_index].clock_info[j].mclk =
2464 rdev->pm.power_state[state_index].clock_info[j].sclk =
2467 rdev->pm.power_state[state_index].clock_info[j].voltage.voltage =
2470 rdev->pm.power_state[state_index].clock_info[j].voltage.vddci =
2488 rdev->pm.power_state[state_index].clock_info[mode_index].sclk = sclk;
2492 rdev->pm.power_state[state_index].clock_info[mode_index].sclk = sclk;
2499 rdev->pm.power_state[state_index].clock_info[mode_index].mclk = mclk;
2500 rdev->pm.power_state[state_index].clock_info[mode_index].sclk = sclk;
2501 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.type =
2508 rdev->pm.power_state[state_index].clock_info[mode_index].mclk = mclk;
2509 rdev->pm.power_state[state_index].clock_info[mode_index].sclk = sclk;
2510 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.type =
2512 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.voltage =
2514 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.vddci =
2521 rdev->pm.power_state[state_index].clock_info[mode_index].mclk = mclk;
2522 rdev->pm.power_state[state_index].clock_info[mode_index].sclk = sclk;
2523 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.type =
2525 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.voltage =
2527 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.vddci =
2534 rdev->pm.power_state[state_index].clock_info[mode_index].mclk = mclk;
2535 rdev->pm.power_state[state_index].clock_info[mode_index].sclk = sclk;
2536 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.type =
2538 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.voltage =
2543 switch (rdev->pm.power_state[state_index].clock_info[mode_index].voltage.voltage) {
2553 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.voltage,
2555 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.voltage = vddc;
2563 if (rdev->pm.power_state[state_index].clock_info[mode_index].sclk == 0)
2567 if ((rdev->pm.power_state[state_index].clock_info[mode_index].mclk == 0) ||
2568 (rdev->pm.power_state[state_index].clock_info[mode_index].sclk == 0))
2578 union pplib_power_state *power_state;
2596 rdev->pm.power_state = kcalloc(power_info->pplib.ucNumStates,
2599 if (!rdev->pm.power_state)
2604 power_state = (union pplib_power_state *)
2611 (power_state->v1.ucNonClockStateIndex *
2613 rdev->pm.power_state[i].clock_info =
2618 if (!rdev->pm.power_state[i].clock_info)
2625 (power_state->v1.ucClockStateIndices[j] *
2634 rdev->pm.power_state[state_index].clock_info[0].mclk =
2636 rdev->pm.power_state[state_index].clock_info[0].sclk =
2640 rdev->pm.power_state[state_index].num_clock_modes = mode_index;
2649 if (rdev->pm.power_state[i].num_clock_modes > 1)
2650 rdev->pm.power_state[i].clock_info[0].flags |=
2655 rdev->pm.power_state[0].type =
2658 rdev->pm.power_state[0].default_clock_mode =
2659 &rdev->pm.power_state[0].clock_info[0];
2668 union pplib_power_state *power_state;
2699 rdev->pm.power_state = kcalloc(state_array->ucNumEntries,
2702 if (!rdev->pm.power_state)
2707 power_state = (union pplib_power_state *)power_state_offset;
2708 non_clock_array_index = power_state->v2.nonClockInfoIndex;
2711 rdev->pm.power_state[i].clock_info =
2712 kcalloc(power_state->v2.ucNumDPMLevels ?
2713 power_state->v2.ucNumDPMLevels : 1,
2716 if (!rdev->pm.power_state[i].clock_info)
2718 if (power_state->v2.ucNumDPMLevels) {
2719 for (j = 0; j < power_state->v2.ucNumDPMLevels; j++) {
2720 clock_array_index = power_state->v2.clockInfoIndex[j];
2730 rdev->pm.power_state[state_index].clock_info[0].mclk =
2732 rdev->pm.power_state[state_index].clock_info[0].sclk =
2736 rdev->pm.power_state[state_index].num_clock_modes = mode_index;
2742 power_state_offset += 2 + power_state->v2.ucNumDPMLevels;
2746 if (rdev->pm.power_state[i].num_clock_modes > 1)
2747 rdev->pm.power_state[i].clock_info[0].flags |=
2752 rdev->pm.power_state[0].type =
2755 rdev->pm.power_state[0].default_clock_mode =
2756 &rdev->pm.power_state[0].clock_info[0];
2792 rdev->pm.power_state = kzalloc(sizeof(struct radeon_power_state), GFP_KERNEL);
2793 if (rdev->pm.power_state) {
2794 rdev->pm.power_state[0].clock_info =
2798 if (rdev->pm.power_state[0].clock_info) {
2800 rdev->pm.power_state[state_index].type =
2802 rdev->pm.power_state[state_index].num_clock_modes = 1;
2803 rdev->pm.power_state[state_index].clock_info[0].mclk = rdev->clock.default_mclk;
2804 rdev->pm.power_state[state_index].clock_info[0].sclk = rdev->clock.default_sclk;
2805 rdev->pm.power_state[state_index].default_clock_mode =
2806 &rdev->pm.power_state[state_index].clock_info[0];
2807 rdev->pm.power_state[state_index].clock_info[0].voltage.type = VOLTAGE_NONE;
2808 rdev->pm.power_state[state_index].pcie_lanes = 16;
2810 rdev->pm.power_state[state_index].flags = 0;
2822 rdev->pm.power_state[rdev->pm.default_power_state_index].clock_info[0].voltage.voltage;