drm/radeon/r600_dma.c

34  * to the 3D engine (ring buffer, IBs, etc.), but the
46  * @ring: radeon ring pointer
51 			   struct radeon_ring *ring)
56 		rptr = rdev->wb.wb[ring->rptr_offs/4];
67  * @ring: radeon ring pointer
72 			   struct radeon_ring *ring)
81  * @ring: radeon ring pointer
86 		       struct radeon_ring *ring)
88 	WREG32(DMA_RB_WPTR, (ring->wptr << 2) & 0x3fffc);
108 	rdev->ring[R600_RING_TYPE_DMA_INDEX].ready = false;
116  * Set up the DMA ring buffer and enable it. (r6xx-evergreen).
121 	struct radeon_ring *ring = &rdev->ring[R600_RING_TYPE_DMA_INDEX];
129 	/* Set ring buffer size in dwords */
130 	rb_bufsz = order_base_2(ring->ring_size / 4);
137 	/* Initialize the ring buffer's read and write pointers */
150 	WREG32(DMA_RB_BASE, ring->gpu_addr >> 8);
166 	ring->wptr = 0;
167 	WREG32(DMA_RB_WPTR, ring->wptr << 2);
171 	ring->ready = true;
173 	r = radeon_ring_test(rdev, R600_RING_TYPE_DMA_INDEX, ring);
175 		ring->ready = false;
190  * Stop the async dma engine and free the ring (r6xx-evergreen).
195 	radeon_ring_fini(rdev, &rdev->ring[R600_RING_TYPE_DMA_INDEX]);
202  * @ring: radeon_ring structure holding ring information
207 bool r600_dma_is_lockup(struct radeon_device *rdev, struct radeon_ring *ring)
212 		radeon_ring_lockup_update(rdev, ring);
215 	return radeon_ring_test_lockup(rdev, ring);
223  * @ring: radeon_ring structure holding ring information
230 		       struct radeon_ring *ring)
238 	if (ring->idx == R600_RING_TYPE_DMA_INDEX)
248 	r = radeon_ring_lock(rdev, ring, 4);
250 		DRM_ERROR("radeon: dma failed to lock ring %d (%d).\n", ring->idx, r);
253 	radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_WRITE, 0, 0, 1));
254 	radeon_ring_write(ring, lower_32_bits(gpu_addr));
255 	radeon_ring_write(ring, upper_32_bits(gpu_addr) & 0xff);
256 	radeon_ring_write(ring, 0xDEADBEEF);
257 	radeon_ring_unlock_commit(rdev, ring, false);
267 		DRM_INFO("ring test on %d succeeded in %d usecs\n", ring->idx, i);
269 		DRM_ERROR("radeon: ring %d test failed (0x%08X)\n",
270 			  ring->idx, tmp);
277  * r600_dma_fence_ring_emit - emit a fence on the DMA ring
282  * Add a DMA fence packet to the ring to write
289 	struct radeon_ring *ring = &rdev->ring[fence->ring];
290 	u64 addr = rdev->fence_drv[fence->ring].gpu_addr;
293 	radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_FENCE, 0, 0, 0));
294 	radeon_ring_write(ring, addr & 0xfffffffc);
295 	radeon_ring_write(ring, (upper_32_bits(addr) & 0xff));
296 	radeon_ring_write(ring, lower_32_bits(fence->seq));
298 	radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_TRAP, 0, 0, 0));
302  * r600_dma_semaphore_ring_emit - emit a semaphore on the dma ring
305  * @ring: radeon_ring structure holding ring information
309  * Add a DMA semaphore packet to the ring wait on or signal
313 				  struct radeon_ring *ring,
320 	radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_SEMAPHORE, 0, s, 0));
321 	radeon_ring_write(ring, addr & 0xfffffffc);
322 	radeon_ring_write(ring, upper_32_bits(addr) & 0xff);
331  * @ring: radeon_ring structure holding ring information
333  * Test a simple IB in the DMA ring (r6xx-SI).
336 int r600_dma_ib_test(struct radeon_device *rdev, struct radeon_ring *ring)
345 	if (ring->idx == R600_RING_TYPE_DMA_INDEX)
352 	r = radeon_ib_get(rdev, ring->idx, &ib, NULL, 256);
387 		DRM_INFO("ib test on ring %d succeeded in %u usecs\n", ib.fence->ring, i);
402  * Schedule an IB in the DMA ring (r6xx-r7xx).
406 	struct radeon_ring *ring = &rdev->ring[ib->ring];
409 		u32 next_rptr = ring->wptr + 4;
413 		radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_WRITE, 0, 0, 1));
414 		radeon_ring_write(ring, ring->next_rptr_gpu_addr & 0xfffffffc);
415 		radeon_ring_write(ring, upper_32_bits(ring->next_rptr_gpu_addr) & 0xff);
416 		radeon_ring_write(ring, next_rptr);
419 	/* The indirect buffer packet must end on an 8 DW boundary in the DMA ring.
422 	while ((ring->wptr & 7) != 5)
423 		radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_NOP, 0, 0, 0));
424 	radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_INDIRECT_BUFFER, 0, 0, 0));
425 	radeon_ring_write(ring, (ib->gpu_addr & 0xFFFFFFE0));
426 	radeon_ring_write(ring, (ib->length_dw << 16) | (upper_32_bits(ib->gpu_addr) & 0xFF));
451 	struct radeon_ring *ring = &rdev->ring[ring_index];
460 	r = radeon_ring_lock(rdev, ring, num_loops * 4 + 8);
468 	radeon_sync_rings(rdev, &sync, ring->idx);
475 		radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_COPY, 0, 0, cur_size_in_dw));
476 		radeon_ring_write(ring, dst_offset & 0xfffffffc);
477 		radeon_ring_write(ring, src_offset & 0xfffffffc);
478 		radeon_ring_write(ring, (((upper_32_bits(dst_offset) & 0xff) << 16) |
484 	r = radeon_fence_emit(rdev, &fence, ring->idx);
486 		radeon_ring_unlock_undo(rdev, ring);
491 	radeon_ring_unlock_commit(rdev, ring, false);