Lines Matching refs:track
43 /* value we track */
299 static void r600_cs_track_init(struct r600_cs_track *track)
304 track->sq_config = DX9_CONSTS;
306 track->cb_color_base_last[i] = 0;
307 track->cb_color_size[i] = 0;
308 track->cb_color_size_idx[i] = 0;
309 track->cb_color_info[i] = 0;
310 track->cb_color_view[i] = 0xFFFFFFFF;
311 track->cb_color_bo[i] = NULL;
312 track->cb_color_bo_offset[i] = 0xFFFFFFFF;
313 track->cb_color_bo_mc[i] = 0xFFFFFFFF;
314 track->cb_color_frag_bo[i] = NULL;
315 track->cb_color_frag_offset[i] = 0xFFFFFFFF;
316 track->cb_color_tile_bo[i] = NULL;
317 track->cb_color_tile_offset[i] = 0xFFFFFFFF;
318 track->cb_color_mask[i] = 0xFFFFFFFF;
320 track->is_resolve = false;
321 track->nsamples = 16;
322 track->log_nsamples = 4;
323 track->cb_target_mask = 0xFFFFFFFF;
324 track->cb_shader_mask = 0xFFFFFFFF;
325 track->cb_dirty = true;
326 track->db_bo = NULL;
327 track->db_bo_mc = 0xFFFFFFFF;
329 track->db_depth_info = 7 | (1 << 25);
330 track->db_depth_view = 0xFFFFC000;
331 track->db_depth_size = 0xFFFFFFFF;
332 track->db_depth_size_idx = 0;
333 track->db_depth_control = 0xFFFFFFFF;
334 track->db_dirty = true;
335 track->htile_bo = NULL;
336 track->htile_offset = 0xFFFFFFFF;
337 track->htile_surface = 0;
340 track->vgt_strmout_size[i] = 0;
341 track->vgt_strmout_bo[i] = NULL;
342 track->vgt_strmout_bo_offset[i] = 0xFFFFFFFF;
343 track->vgt_strmout_bo_mc[i] = 0xFFFFFFFF;
345 track->streamout_dirty = true;
346 track->sx_misc_kill_all_prims = false;
351 struct r600_cs_track *track = p->track;
360 unsigned nsamples = track->is_resolve && i == 1 ? 1 : track->nsamples;
362 format = G_0280A0_FORMAT(track->cb_color_info[i]);
366 i, track->cb_color_info[i]);
370 pitch = (G_028060_PITCH_TILE_MAX(track->cb_color_size[i]) + 1) * 8;
371 slice_tile_max = G_028060_SLICE_TILE_MAX(track->cb_color_size[i]) + 1;
376 array_mode = G_0280A0_ARRAY_MODE(track->cb_color_info[i]);
378 base_offset = track->cb_color_bo_mc[i] + track->cb_color_bo_offset[i];
380 array_check.group_size = track->group_size;
381 array_check.nbanks = track->nbanks;
382 array_check.npipes = track->npipes;
388 G_0280A0_ARRAY_MODE(track->cb_color_info[i]), i,
389 track->cb_color_info[i]);
406 G_0280A0_ARRAY_MODE(track->cb_color_info[i]), i,
407 track->cb_color_info[i]);
434 tmp += track->cb_color_view[i] & 0xFF;
438 tmp += G_028080_SLICE_MAX(track->cb_color_view[i]) * tmp;
441 if ((tmp + track->cb_color_bo_offset[i]) > radeon_bo_size(track->cb_color_bo[i])) {
452 track->cb_color_bo_offset[i], tmp,
453 radeon_bo_size(track->cb_color_bo[i]),
466 ib[track->cb_color_size_idx[i]] = tmp;
469 switch (G_0280A0_TILE_MODE(track->cb_color_info[i])) {
473 if (track->nsamples > 1) {
474 uint32_t tile_max = G_028100_FMASK_TILE_MAX(track->cb_color_mask[i]);
477 uint32_t bytes = track->nsamples * track->log_nsamples * 8 * (tile_max + 1);
479 if (bytes + track->cb_color_frag_offset[i] >
480 radeon_bo_size(track->cb_color_frag_bo[i])) {
484 track->cb_color_frag_offset[i],
485 radeon_bo_size(track->cb_color_frag_bo[i]));
492 uint32_t block_max = G_028100_CMASK_BLOCK_MAX(track->cb_color_mask[i]);
497 if (bytes + track->cb_color_tile_offset[i] >
498 radeon_bo_size(track->cb_color_tile_bo[i])) {
502 track->cb_color_tile_offset[i],
503 radeon_bo_size(track->cb_color_tile_bo[i]));
517 struct r600_cs_track *track = p->track;
528 if (track->db_bo == NULL) {
532 switch (G_028010_FORMAT(track->db_depth_info)) {
547 dev_warn(p->dev, "z/stencil with invalid format %d\n", G_028010_FORMAT(track->db_depth_info));
550 if ((track->db_depth_size & 0xFFFFFC00) == 0xFFFFFC00) {
551 if (!track->db_depth_size_idx) {
555 tmp = radeon_bo_size(track->db_bo) - track->db_offset;
559 track->db_depth_size, bpe, track->db_offset,
560 radeon_bo_size(track->db_bo));
563 ib[track->db_depth_size_idx] = S_028000_SLICE_TILE_MAX(tmp - 1) | (track->db_depth_size & 0x3FF);
566 pitch = (G_028000_PITCH_TILE_MAX(track->db_depth_size) + 1) * 8;
567 slice_tile_max = G_028000_SLICE_TILE_MAX(track->db_depth_size) + 1;
572 base_offset = track->db_bo_mc + track->db_offset;
573 array_mode = G_028010_ARRAY_MODE(track->db_depth_info);
575 array_check.group_size = track->group_size;
576 array_check.nbanks = track->nbanks;
577 array_check.npipes = track->npipes;
578 array_check.nsamples = track->nsamples;
583 G_028010_ARRAY_MODE(track->db_depth_info),
584 track->db_depth_info);
596 G_028010_ARRAY_MODE(track->db_depth_info),
597 track->db_depth_info);
617 ntiles = G_028000_SLICE_TILE_MAX(track->db_depth_size) + 1;
618 nviews = G_028004_SLICE_MAX(track->db_depth_view) + 1;
619 tmp = ntiles * bpe * 64 * nviews * track->nsamples;
620 if ((tmp + track->db_offset) > radeon_bo_size(track->db_bo)) {
623 track->db_depth_size, ntiles, nviews, bpe, tmp + track->db_offset,
624 radeon_bo_size(track->db_bo));
630 if (G_028010_TILE_SURFACE_ENABLE(track->db_depth_info)) {
634 if (track->htile_bo == NULL) {
636 __func__, __LINE__, track->db_depth_info);
639 if ((track->db_depth_size & 0xFFFFFC00) == 0xFFFFFC00) {
641 __func__, __LINE__, track->db_depth_size);
647 if (G_028D24_LINEAR(track->htile_surface)) {
651 nby = round_up(nby, track->npipes * 8);
657 switch (track->npipes) {
680 __func__, __LINE__, track->npipes);
688 size = roundup(nbx * nby * 4, track->npipes * (2 << 10));
689 size += track->htile_offset;
691 if (size > radeon_bo_size(track->htile_bo)) {
693 __func__, __LINE__, radeon_bo_size(track->htile_bo),
699 track->db_dirty = false;
705 struct r600_cs_track *track = p->track;
714 if (track->streamout_dirty && track->vgt_strmout_en) {
716 if (track->vgt_strmout_buffer_en & (1 << i)) {
717 if (track->vgt_strmout_bo[i]) {
718 u64 offset = (u64)track->vgt_strmout_bo_offset[i] +
719 (u64)track->vgt_strmout_size[i];
720 if (offset > radeon_bo_size(track->vgt_strmout_bo[i])) {
723 radeon_bo_size(track->vgt_strmout_bo[i]));
732 track->streamout_dirty = false;
735 if (track->sx_misc_kill_all_prims)
741 if (track->cb_dirty) {
742 tmp = track->cb_target_mask;
745 if (track->is_resolve) {
750 u32 format = G_0280A0_FORMAT(track->cb_color_info[i]);
755 if (track->cb_color_bo[i] == NULL) {
757 __func__, __LINE__, track->cb_target_mask, track->cb_shader_mask, i);
766 track->cb_dirty = false;
770 if (track->db_dirty &&
771 G_028010_FORMAT(track->db_depth_info) != V_028010_DEPTH_INVALID &&
772 (G_028800_STENCIL_ENABLE(track->db_depth_control) ||
773 G_028800_Z_ENABLE(track->db_depth_control))) {
968 struct r600_cs_track *track = (struct r600_cs_track *)p->track;
1023 track->sq_config = radeon_get_ib_value(p, idx);
1026 track->db_depth_control = radeon_get_ib_value(p, idx);
1027 track->db_dirty = true;
1038 track->db_depth_info = radeon_get_ib_value(p, idx);
1040 track->db_depth_info &= C_028010_ARRAY_MODE;
1043 track->db_depth_info |= S_028010_ARRAY_MODE(V_028010_ARRAY_2D_TILED_THIN1);
1046 track->db_depth_info |= S_028010_ARRAY_MODE(V_028010_ARRAY_1D_TILED_THIN1);
1049 track->db_depth_info = radeon_get_ib_value(p, idx);
1051 track->db_dirty = true;
1054 track->db_depth_view = radeon_get_ib_value(p, idx);
1055 track->db_dirty = true;
1058 track->db_depth_size = radeon_get_ib_value(p, idx);
1059 track->db_depth_size_idx = idx;
1060 track->db_dirty = true;
1063 track->vgt_strmout_en = radeon_get_ib_value(p, idx);
1064 track->streamout_dirty = true;
1067 track->vgt_strmout_buffer_en = radeon_get_ib_value(p, idx);
1068 track->streamout_dirty = true;
1081 track->vgt_strmout_bo_offset[tmp] = radeon_get_ib_value(p, idx) << 8;
1083 track->vgt_strmout_bo[tmp] = reloc->robj;
1084 track->vgt_strmout_bo_mc[tmp] = reloc->gpu_offset;
1085 track->streamout_dirty = true;
1093 track->vgt_strmout_size[tmp] = radeon_get_ib_value(p, idx) * 4;
1094 track->streamout_dirty = true;
1106 track->cb_target_mask = radeon_get_ib_value(p, idx);
1107 track->cb_dirty = true;
1110 track->cb_shader_mask = radeon_get_ib_value(p, idx);
1114 track->log_nsamples = tmp;
1115 track->nsamples = 1 << tmp;
1116 track->cb_dirty = true;
1120 track->is_resolve = tmp == V_028808_SPECIAL_RESOLVE_BOX;
1121 track->cb_dirty = true;
1139 track->cb_color_info[tmp] = radeon_get_ib_value(p, idx);
1142 track->cb_color_info[tmp] |= S_0280A0_ARRAY_MODE(V_0280A0_ARRAY_2D_TILED_THIN1);
1145 track->cb_color_info[tmp] |= S_0280A0_ARRAY_MODE(V_0280A0_ARRAY_1D_TILED_THIN1);
1149 track->cb_color_info[tmp] = radeon_get_ib_value(p, idx);
1151 track->cb_dirty = true;
1162 track->cb_color_view[tmp] = radeon_get_ib_value(p, idx);
1163 track->cb_dirty = true;
1174 track->cb_color_size[tmp] = radeon_get_ib_value(p, idx);
1175 track->cb_color_size_idx[tmp] = idx;
1176 track->cb_dirty = true;
1197 if (!track->cb_color_base_last[tmp]) {
1201 track->cb_color_frag_bo[tmp] = track->cb_color_bo[tmp];
1202 track->cb_color_frag_offset[tmp] = track->cb_color_bo_offset[tmp];
1203 ib[idx] = track->cb_color_base_last[tmp];
1210 track->cb_color_frag_bo[tmp] = reloc->robj;
1211 track->cb_color_frag_offset[tmp] = (u64)ib[idx] << 8;
1214 if (G_0280A0_TILE_MODE(track->cb_color_info[tmp])) {
1215 track->cb_dirty = true;
1228 if (!track->cb_color_base_last[tmp]) {
1232 track->cb_color_tile_bo[tmp] = track->cb_color_bo[tmp];
1233 track->cb_color_tile_offset[tmp] = track->cb_color_bo_offset[tmp];
1234 ib[idx] = track->cb_color_base_last[tmp];
1241 track->cb_color_tile_bo[tmp] = reloc->robj;
1242 track->cb_color_tile_offset[tmp] = (u64)ib[idx] << 8;
1245 if (G_0280A0_TILE_MODE(track->cb_color_info[tmp])) {
1246 track->cb_dirty = true;
1258 track->cb_color_mask[tmp] = radeon_get_ib_value(p, idx);
1259 if (G_0280A0_TILE_MODE(track->cb_color_info[tmp])) {
1260 track->cb_dirty = true;
1278 track->cb_color_bo_offset[tmp] = (u64)radeon_get_ib_value(p, idx) << 8;
1280 track->cb_color_base_last[tmp] = ib[idx];
1281 track->cb_color_bo[tmp] = reloc->robj;
1282 track->cb_color_bo_mc[tmp] = reloc->gpu_offset;
1283 track->cb_dirty = true;
1292 track->db_offset = radeon_get_ib_value(p, idx) << 8;
1294 track->db_bo = reloc->robj;
1295 track->db_bo_mc = reloc->gpu_offset;
1296 track->db_dirty = true;
1305 track->htile_offset = (u64)radeon_get_ib_value(p, idx) << 8;
1307 track->htile_bo = reloc->robj;
1308 track->db_dirty = true;
1311 track->htile_surface = radeon_get_ib_value(p, idx);
1314 track->db_dirty = true;
1387 track->sx_misc_kill_all_prims = (radeon_get_ib_value(p, idx) & 0x1) != 0;
1476 struct r600_cs_track *track = p->track;
1516 array_check.group_size = track->group_size;
1517 array_check.nbanks = track->nbanks;
1518 array_check.npipes = track->npipes;
1630 struct r600_cs_track *track;
1638 track = (struct r600_cs_track *)p->track;
2024 if (track->sq_config & DX9_CONSTS) {
2102 if (reloc->robj != track->vgt_strmout_bo[idx_value]) {
2108 if (offset != track->vgt_strmout_bo_offset[idx_value]) {
2110 offset, track->vgt_strmout_bo_offset[idx_value]);
2271 struct r600_cs_track *track;
2274 if (p->track == NULL) {
2276 track = kzalloc(sizeof(*track), GFP_KERNEL);
2277 if (track == NULL)
2279 r600_cs_track_init(track);
2281 track->npipes = p->rdev->config.r600.tiling_npipes;
2282 track->nbanks = p->rdev->config.r600.tiling_nbanks;
2283 track->group_size = p->rdev->config.r600.tiling_group_size;
2285 track->npipes = p->rdev->config.rv770.tiling_npipes;
2286 track->nbanks = p->rdev->config.rv770.tiling_nbanks;
2287 track->group_size = p->rdev->config.rv770.tiling_group_size;
2289 p->track = track;
2294 kfree(p->track);
2295 p->track = NULL;
2310 kfree(p->track);
2311 p->track = NULL;
2315 kfree(p->track);
2316 p->track = NULL;
2326 kfree(p->track);
2327 p->track = NULL;