drm/radeon/r600.c

3315 	rdev->ih.ring_obj = NULL;
3473 	rdev->ih.ring_size = ring_size;
3474 	rdev->ih.ptr_mask = rdev->ih.ring_size - 1;
3475 	rdev->ih.rptr = 0;
3483 	if (rdev->ih.ring_obj == NULL) {
3484 		r = radeon_bo_create(rdev, rdev->ih.ring_size,
3487 				     NULL, NULL, &rdev->ih.ring_obj);
3489 			DRM_ERROR("radeon: failed to create ih ring buffer (%d).\n", r);
3492 		r = radeon_bo_reserve(rdev->ih.ring_obj, false);
3495 		r = radeon_bo_pin(rdev->ih.ring_obj,
3497 				  &rdev->ih.gpu_addr);
3499 			radeon_bo_unreserve(rdev->ih.ring_obj);
3500 			DRM_ERROR("radeon: failed to pin ih ring buffer (%d).\n", r);
3503 		r = radeon_bo_kmap(rdev->ih.ring_obj,
3504 				   (void **)&rdev->ih.ring);
3505 		radeon_bo_unreserve(rdev->ih.ring_obj);
3507 			DRM_ERROR("radeon: failed to map ih ring buffer (%d).\n", r);
3517 	if (rdev->ih.ring_obj) {
3518 		r = radeon_bo_reserve(rdev->ih.ring_obj, false);
3520 			radeon_bo_kunmap(rdev->ih.ring_obj);
3521 			radeon_bo_unpin(rdev->ih.ring_obj);
3522 			radeon_bo_unreserve(rdev->ih.ring_obj);
3524 		radeon_bo_unref(&rdev->ih.ring_obj);
3525 		rdev->ih.ring = NULL;
3526 		rdev->ih.ring_obj = NULL;
3599 	rdev->ih.enabled = true;
3614 	rdev->ih.enabled = false;
3615 	rdev->ih.rptr = 0;
3707 	WREG32(IH_RB_BASE, rdev->ih.gpu_addr >> 8);
3708 	rb_bufsz = order_base_2(rdev->ih.ring_size / 4);
3775 	/* don't enable anything if the ih is disabled */
3776 	if (!rdev->ih.enabled) {
4053 			 wptr, rdev->ih.rptr, (wptr + 16) & rdev->ih.ptr_mask);
4054 		rdev->ih.rptr = (wptr + 16) & rdev->ih.ptr_mask;
4059 	return (wptr & rdev->ih.ptr_mask);
4102 	if (!rdev->ih.enabled || rdev->shutdown)
4113 	if (atomic_xchg(&rdev->ih.lock, 1))
4116 	rptr = rdev->ih.rptr;
4128 		src_id = le32_to_cpu(rdev->ih.ring[ring_index]) & 0xff;
4129 		src_data = le32_to_cpu(rdev->ih.ring[ring_index + 1]) & 0xfffffff;
4321 		rptr &= rdev->ih.ptr_mask;
4330 	rdev->ih.rptr = rptr;
4331 	atomic_set(&rdev->ih.lock, 0);